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Modify BoundsSan to improve debuggability #65972
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py | ||
; RUN: opt < %s -passes=bounds-checking -bounds-checking-unique-traps -S | FileCheck %s | ||
target datalayout = "e-p:64:64:64-p1:16:16:16-p2:64:64:64:48-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" | ||
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declare noalias ptr @malloc(i64) nounwind allocsize(0) | ||
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define void @f() nounwind { | ||
; CHECK-LABEL: @f( | ||
; CHECK-NEXT: [[TMP1:%.*]] = tail call ptr @malloc(i64 32) | ||
; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 8 | ||
; CHECK-NEXT: br label [[TRAP:%.*]] | ||
; CHECK: 2: | ||
; CHECK-NEXT: store i32 3, ptr [[IDX]], align 4 | ||
; CHECK-NEXT: [[TMP3:%.*]] = tail call ptr @malloc(i64 32) | ||
; CHECK-NEXT: [[IDX2:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8 | ||
; CHECK-NEXT: br label [[TRAP1:%.*]] | ||
; CHECK: 4: | ||
; CHECK-NEXT: store i32 3, ptr [[IDX2]], align 4 | ||
; CHECK-NEXT: [[TMP5:%.*]] = tail call ptr @malloc(i64 32) | ||
; CHECK-NEXT: [[IDX3:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 8 | ||
; CHECK-NEXT: br label [[TRAP2:%.*]] | ||
; CHECK: 6: | ||
; CHECK-NEXT: store i32 3, ptr [[IDX3]], align 4 | ||
; CHECK-NEXT: ret void | ||
; CHECK: trap: | ||
; CHECK-NEXT: call void @llvm.ubsantrap(i8 3) #[[ATTR3:[0-9]+]] | ||
; CHECK-NEXT: unreachable | ||
; CHECK: trap1: | ||
; CHECK-NEXT: call void @llvm.ubsantrap(i8 5) #[[ATTR3]] | ||
; CHECK-NEXT: unreachable | ||
; CHECK: trap2: | ||
; CHECK-NEXT: call void @llvm.ubsantrap(i8 7) #[[ATTR3]] | ||
; CHECK-NEXT: unreachable | ||
; | ||
%1 = tail call ptr @malloc(i64 32) | ||
%idx = getelementptr inbounds i32, ptr %1, i64 8 | ||
store i32 3, ptr %idx, align 4 | ||
%2 = tail call ptr @malloc(i64 32) | ||
%idx2 = getelementptr inbounds i32, ptr %2, i64 8 | ||
store i32 3, ptr %idx2, align 4 | ||
%3 = tail call ptr @malloc(i64 32) | ||
%idx3 = getelementptr inbounds i32, ptr %3, i64 8 | ||
store i32 3, ptr %idx3, align 4 | ||
ret void | ||
} |
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; RUN: llc -O3 -mtriple arm64-linux -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ASM | ||
; What this test does is check that even with nomerge, the functions still get merged in | ||
; compiled code as the ubsantrap call gets lowered to a single instruction: brk. | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. you don't change MC, so I don't think we need the test here However we need a test in llvm-project/llvm/test/Instrumentation/BoundsChecking/ There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I understood your comment on the Phabricator diff as a request for this test:
I will also add a test in |
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@B = dso_local global [10 x i8] zeroinitializer, align 1 | ||
@B2 = dso_local global [10 x i8] zeroinitializer, align 1 | ||
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; Function Attrs: noinline nounwind uwtable | ||
define dso_local void @f8(i32 noundef %i, i32 noundef %k) #0 { | ||
entry: | ||
; CHECK-ASM: cmp x8, #10 | ||
; CHECK-ASM: b.hi .LBB0_5 | ||
; CHECK-ASM: // %bb.1: // %entry | ||
; CHECK-ASM: mov w9, #10 // =0xa | ||
; CHECK-ASM: sub x9, x9, x8 | ||
; CHECK-ASM: cbz x9, .LBB0_5 | ||
; CHECK-ASM: // %bb.2: | ||
; CHECK-ASM: ldrsw x9, [sp, #8] | ||
; CHECK-ASM: adrp x10, B | ||
; CHECK-ASM: add x10, x10, :lo12:B | ||
; CHECK-ASM: strb wzr, [x10, x8] | ||
; CHECK-ASM: cmp x9, #10 | ||
; CHECK-ASM: b.hi .LBB0_5 | ||
; CHECK-ASM: // %bb.3: | ||
; CHECK-ASM: mov w8, #10 // =0xa | ||
; CHECK-ASM: sub x8, x8, x9 | ||
; CHECK-ASM: cbz x8, .LBB0_5 | ||
; CHECK-ASM: // %bb.4: | ||
; CHECK-ASM: adrp x8, B2 | ||
; CHECK-ASM: add x8, x8, :lo12:B2 | ||
; CHECK-ASM: strb wzr, [x8, x9] | ||
; CHECK-ASM: add sp, sp, #16 | ||
; CHECK-ASM: .cfi_def_cfa_offset 0 | ||
; CHECK-ASM: ret | ||
; CHECK-ASM: .LBB0_5: // %trap3 | ||
; CHECK-ASM: .cfi_restore_state | ||
; CHECK-ASM: brk #0x1 | ||
%i.addr = alloca i32, align 4 | ||
%k.addr = alloca i32, align 4 | ||
store i32 %i, ptr %i.addr, align 4 | ||
store i32 %k, ptr %k.addr, align 4 | ||
%0 = load i32, ptr %i.addr, align 4 | ||
%idxprom = sext i32 %0 to i64 | ||
%1 = add i64 0, %idxprom | ||
%arrayidx = getelementptr inbounds [10 x i8], ptr @B, i64 0, i64 %idxprom | ||
%2 = sub i64 10, %1 | ||
%3 = icmp ult i64 10, %1 | ||
%4 = icmp ult i64 %2, 1 | ||
%5 = or i1 %3, %4 | ||
br i1 %5, label %trap, label %6 | ||
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6: ; preds = %entry | ||
store i8 0, ptr %arrayidx, align 1 | ||
%7 = load i32, ptr %k.addr, align 4 | ||
%idxprom1 = sext i32 %7 to i64 | ||
%8 = add i64 0, %idxprom1 | ||
%arrayidx2 = getelementptr inbounds [10 x i8], ptr @B2, i64 0, i64 %idxprom1 | ||
%9 = sub i64 10, %8 | ||
%10 = icmp ult i64 10, %8 | ||
%11 = icmp ult i64 %9, 1 | ||
%12 = or i1 %10, %11 | ||
br i1 %12, label %trap3, label %13 | ||
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13: ; preds = %6 | ||
store i8 0, ptr %arrayidx2, align 1 | ||
ret void | ||
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trap: ; preds = %entry | ||
call void @llvm.trap() #2 | ||
unreachable | ||
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trap3: ; preds = %6 | ||
call void @llvm.trap() #2 | ||
unreachable | ||
} | ||
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; Function Attrs: cold noreturn nounwind memory(inaccessiblemem: write) | ||
declare void @llvm.trap() #1 | ||
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attributes #0 = { noinline nounwind uwtable } | ||
attributes #1 = { cold noreturn nounwind memory(inaccessiblemem: write) } | ||
attributes #2 = { noreturn nounwind nomerge } |
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