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Revert Add host-supports-nvptx requirement to lit tests (#66102 and #66129) #66225

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Merged
merged 2 commits into from
Sep 13, 2023
Merged

Revert Add host-supports-nvptx requirement to lit tests (#66102 and #66129) #66225

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113acfa
Revert "Add host-supports-nvptx requirement to lit tests (#66129)"
frgossen Sep 13, 2023
22cb70e
Revert "Add host-supports-nvptx requirement to lit tests (#66102)"
frgossen Sep 13, 2023
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2 changes: 0 additions & 2 deletions mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/dump-ptx.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm -debug-only=serialize-to-isa \
// RUN: 2>&1 | FileCheck %s
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1 change: 0 additions & 1 deletion mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec-const.mlir
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// REQUIRES: host-supports-nvptx
//
// NOTE: this test requires gpu-sm80
//
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1 change: 0 additions & 1 deletion mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec.mlir
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// REQUIRES: host-supports-nvptx
//
// NOTE: this test requires gpu-sm80
//
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2 changes: 0 additions & 2 deletions mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
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// REQUIRES: host-supports-nvptx

//
// NOTE: this test requires gpu-sm80
//
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2 changes: 0 additions & 2 deletions mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s -test-vector-warp-distribute="hoist-uniform distribute-transfer-write propagate-distribution" -canonicalize |\
// RUN: mlir-opt -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if |\
// RUN: mlir-opt -lower-affine -convert-vector-to-scf -convert-scf-to-cf -convert-vector-to-llvm \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir
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// REQUIRES: host-supports-nvptx

// Run the test cases without distributing ops to test default lowering. Run
// everything on the same thread.
// RUN: mlir-opt %s -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if -canonicalize | \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f16-f16-accum.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: -test-transform-dialect-interpreter \
// RUN: -test-transform-dialect-erase-schedule \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f32.mlir
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// REQUIRES: host-supports-nvptx
//
// RUN: mlir-opt %s \
// RUN: -test-transform-dialect-interpreter \
// RUN: | FileCheck %s --check-prefix=CHECK-MMA-SYNC
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm="cubin-chip=sm_70" \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32-bare-ptr.mlir
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// REQUIRES: host-supports-nvptx

// Tests memref bare pointer lowering convention both host side and kernel-side;
// this works for only statically shaped memrefs.
// Similar to the wmma-matmul-f32 but but with the memref bare pointer lowering convention.
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm="cubin-chip=sm_70" \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-and.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-max.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-min.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-op.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-or.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-region.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/all-reduce-xor.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/async.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -gpu-kernel-outlining \
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm),nvvm-attach-target)' \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/gpu-to-cubin.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/multiple-all-reduce.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/printf.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/shuffle.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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2 changes: 0 additions & 2 deletions .../Integration/GPU/CUDA/sm90/transform-dialect/tma_load_64x8_8x128_noswizzle-transform.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: -test-transform-dialect-interpreter \
// RUN: -test-transform-dialect-erase-schedule \
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2 changes: 0 additions & 2 deletions mlir/test/Integration/GPU/CUDA/two-modules.mlir
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// REQUIRES: host-supports-nvptx

// RUN: mlir-opt %s \
// RUN: | mlir-opt -test-lower-to-nvvm \
// RUN: | mlir-cpu-runner \
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