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[RISCV] Truncate constants to eltwidth before checking simm5 when con… #67062

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Merged
merged 1 commit into from
Sep 22, 2023
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[RISCV] Truncate constants to eltwidth before checking simm5 when con… #67062

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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14435,7 +14435,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
// patterns on rv32..
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
(!Const || Const->isZero() || !isInt<5>(Const->getSExtValue())))
(!Const || Const->isZero() ||
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Why is that SimplifyDemandedLowBitsHelper just above can't catch this case? If only the low bits are demanded - which I think is what you're suggesting here - shouldn't that have folded the constant?

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I don't think the DemandedBits will turn a zero extended i64 constant into a sign extended i64 constant if the upper bits aren't used. Is that what you're suggesting?

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That was the question I'd asked, but to reframe it, why not go ahead and convert the constant to the sign extended form eagerly? Even if we don't convert to the vmv_s_x, isn't that a reasonable canonicalization of the vmv_v_x?

p.s. I'm completely fine with this landing as is, just suggesting a potentially cleaner way of doing it.

!Const->getAPIntValue().sextOrTrunc(EltWidth).isSignedIntN(5)))
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);

break;
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13 changes: 13 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
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Expand Up @@ -781,3 +781,16 @@ define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) {
%res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 9, i32 4, i32 11, i32 6, i32 13, i32 8, i32 15>
ret <8 x i8> %res
}

; Make sure we use a vmv.v.i to load the mask constant.
define <8 x i32> @shuffle_v8i32_2(<8 x i32> %x, <8 x i32> %y) {
; CHECK-LABEL: shuffle_v8i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, -13
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Without this patch we get li a0, 243 and vmv.s.x v0, a0

; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
ret <8 x i32> %s
}