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[AMDGPU] Fold uniform readfirstlane + cndmask #70188

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[AMDGPU] Fold uniform readfirstlane + cndmask #70188

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c128818
[AMDGPU] Fold uniform readfirstlane + cndmask
Pierre-vh Oct 25, 2023
e57d6e8
Add null check for RFLSrc
Pierre-vh Oct 25, 2023
5153268
clang-format
Pierre-vh Oct 25, 2023
a72660b
Rework: fold into S_CSELECT instead
Pierre-vh Oct 26, 2023
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81 changes: 81 additions & 0 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,7 @@ class SIFoldOperands : public MachineFunctionPass {
bool foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
bool tryFoldFoldableCopy(MachineInstr &MI,
MachineOperand *&CurrentKnownM0Val) const;
bool tryFoldUniformReadFirstLaneCndMask(MachineInstr &MI) const;

const MachineOperand *isClamp(const MachineInstr &MI) const;
bool tryFoldClamp(MachineInstr &MI);
Expand Down Expand Up @@ -1400,6 +1401,81 @@ bool SIFoldOperands::tryFoldFoldableCopy(
return Changed;
}

// Try to fold the following pattern:
// s_cselect s[2:3], -1, 0
// v_cndmask v0, 0, +-1, s[2:3]
Comment on lines +1405 to +1406
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This pattern is a uniform select. Why would we have selected v_cndmask instead of s_cselect in the first place?

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I think we just have some other patterns like in the ticket that always emit a cndmask, even with a cselect would do the trick. I'll have a closer look.

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I think it's the i32 zext pattern, similar to the i64 zext pattern we fixed.
Last I tried changing it though there were a lot of test changes and not all of them were good. I can try to look again if this patch is not going to land.

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I still feel like this patch is just trying to work around poor instruction selection. Can you put up a patch for changing the i32 zext selection pattern, so we can look at that?

// v_readfirstlane s0, v0
//
// into
//
// s_cselect s0, +-1, 0
bool SIFoldOperands::tryFoldUniformReadFirstLaneCndMask(
MachineInstr &MI) const {
if (MI.getOpcode() != AMDGPU::V_READFIRSTLANE_B32)
return false;

MachineInstr *RFLSrc = MRI->getVRegDef(MI.getOperand(1).getReg());
if (!RFLSrc)
return false;

// We can also have the following pattern:
//
// %2:vreg_64 = REG_SEQUENCE %X:vgpr_32, sub0, %1:sreg_32, sub1
// %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64
//
// In this case we dig into %X or %Y depending on which sub register
// the V_READFIRSTLANE accesses.
if (RFLSrc->isRegSequence()) {
unsigned RFLSubReg = MI.getOperand(1).getSubReg();
if (RFLSrc->getNumOperands() != 5)
return false;

if (RFLSrc->getOperand(2).getImm() == RFLSubReg)
RFLSrc = MRI->getVRegDef(RFLSrc->getOperand(1).getReg());
else if (RFLSrc->getOperand(4).getImm() == RFLSubReg)
RFLSrc = MRI->getVRegDef(RFLSrc->getOperand(3).getReg());
else
return false;
}

// Need e64 to have a SGPR regmask.
if (!RFLSrc || RFLSrc->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
return false;

MachineOperand *Src0 = TII->getNamedOperand(*RFLSrc, AMDGPU::OpName::src0);
MachineOperand *Src1 = TII->getNamedOperand(*RFLSrc, AMDGPU::OpName::src1);
Register Src2 = TII->getNamedOperand(*RFLSrc, AMDGPU::OpName::src2)->getReg();

if (!Src0->isImm() || Src0->getImm() != 0 || !Src1->isImm())
return false;

bool IsSigned = (Src1->getImm() == -1);
if (Src1->getImm() != 1 && !IsSigned)
return false;

MachineInstr *CSel = MRI->getVRegDef(Src2);
if (!CSel || (CSel->getOpcode() != AMDGPU::S_CSELECT_B32 &&
CSel->getOpcode() != AMDGPU::S_CSELECT_B64))
return false;

MachineOperand *CSelSrc0 = TII->getNamedOperand(*CSel, AMDGPU::OpName::src0);
MachineOperand *CSelSrc1 = TII->getNamedOperand(*CSel, AMDGPU::OpName::src1);
// Note: we could also allow any non-zero value for CSelSrc0, and adapt the
// BFE's mask depending on where the first set bit is.
if (!CSelSrc0->isImm() || CSelSrc0->getImm() != -1 || !CSelSrc1->isImm() ||
CSelSrc1->getImm() != 0)
return false;

// Build a S_CSELECT right before the old one so we're sure it uses the same
// SCC def.
BuildMI(*CSel->getParent(), *CSel, MI.getDebugLoc(),
TII->get(AMDGPU::S_CSELECT_B32), MI.getOperand(0).getReg())
.addImm(IsSigned ? -1 : 1)
.addImm(0);
MI.eraseFromParent();
return true;
}

// Clamp patterns are canonically selected to v_max_* instructions, so only
// handle them.
const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
Expand Down Expand Up @@ -2087,6 +2163,11 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
continue;
}

if (tryFoldUniformReadFirstLaneCndMask(MI)) {
Changed = true;
continue;
}

// Saw an unknown clobber of m0, so we no longer know what it is.
if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI))
CurrentKnownM0Val = nullptr;
Expand Down
103 changes: 47 additions & 56 deletions llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1532,15 +1532,13 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
; SI-NEXT: s_lshr_b32 s4, s3, 8
; SI-NEXT: s_and_b32 s5, s3, 0x1ff
; SI-NEXT: s_and_b32 s6, s4, 0xffe
; SI-NEXT: s_and_b32 s4, s4, 0xffe
; SI-NEXT: s_or_b32 s2, s5, s2
; SI-NEXT: s_cmp_lg_u32 s2, 0
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; SI-NEXT: v_readfirstlane_b32 s2, v1
; SI-NEXT: s_cselect_b32 s2, 1, 0
; SI-NEXT: s_bfe_u32 s5, s3, 0xb0014
; SI-NEXT: s_or_b32 s2, s6, s2
; SI-NEXT: s_sub_i32 s6, 0x3f1, s5
; SI-NEXT: s_or_b32 s2, s4, s2
; SI-NEXT: v_med3_i32 v1, s6, 0, 13
; SI-NEXT: s_or_b32 s4, s2, 0x1000
; SI-NEXT: v_readfirstlane_b32 s6, v1
Expand Down Expand Up @@ -1595,15 +1593,13 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s0, s7, 8
; VI-NEXT: s_and_b32 s1, s7, 0x1ff
; VI-NEXT: s_and_b32 s2, s0, 0xffe
; VI-NEXT: s_or_b32 s0, s1, s6
; VI-NEXT: s_cmp_lg_u32 s0, 0
; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; VI-NEXT: v_readfirstlane_b32 s0, v2
; VI-NEXT: s_bfe_u32 s1, s7, 0xb0014
; VI-NEXT: s_and_b32 s0, s0, 0xffe
; VI-NEXT: s_or_b32 s1, s1, s6
; VI-NEXT: s_cmp_lg_u32 s1, 0
; VI-NEXT: s_cselect_b32 s1, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_or_b32 s4, s2, s0
; VI-NEXT: s_or_b32 s4, s0, s1
; VI-NEXT: s_bfe_u32 s1, s7, 0xb0014
; VI-NEXT: s_sub_i32 s2, 0x3f1, s1
; VI-NEXT: v_med3_i32 v2, s2, 0, 13
; VI-NEXT: s_or_b32 s0, s4, 0x1000
Expand Down Expand Up @@ -1657,14 +1653,12 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s0, s7, 8
; GFX9-NEXT: s_and_b32 s1, s7, 0x1ff
; GFX9-NEXT: s_and_b32 s2, s0, 0xffe
; GFX9-NEXT: s_or_b32 s0, s1, s6
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: s_and_b32 s0, s0, 0xffe
; GFX9-NEXT: s_or_b32 s1, s1, s6
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_or_b32 s6, s0, s1
; GFX9-NEXT: s_bfe_u32 s1, s7, 0xb0014
; GFX9-NEXT: s_or_b32 s6, s2, s0
; GFX9-NEXT: s_sub_i32 s2, 0x3f1, s1
; GFX9-NEXT: v_med3_i32 v1, s2, 0, 13
; GFX9-NEXT: s_or_b32 s0, s6, 0x1000
Expand Down Expand Up @@ -1714,63 +1708,60 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x34
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s1, s7, 0x1ff
; GFX11-NEXT: s_lshr_b32 s2, s7, 8
; GFX11-NEXT: s_or_b32 s1, s1, s6
; GFX11-NEXT: s_and_b32 s2, s2, 0xffe
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX11-NEXT: s_bfe_u32 s1, s7, 0xb0014
; GFX11-NEXT: s_sub_i32 s3, 0x3f1, s1
; GFX11-NEXT: s_addk_i32 s1, 0xfc10
; GFX11-NEXT: v_med3_i32 v1, s3, 0, 13
; GFX11-NEXT: v_readfirstlane_b32 s3, v0
; GFX11-NEXT: s_lshl_b32 s8, s1, 12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s6, v1
; GFX11-NEXT: s_or_b32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_or_b32 s3, s2, 0x1000
; GFX11-NEXT: s_or_b32 s8, s2, s8
; GFX11-NEXT: s_lshr_b32 s6, s3, s6
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e64 v0, v1, s6
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, s3, v0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-NEXT: s_bfe_u32 s3, s7, 0xb0014
; GFX11-NEXT: s_or_b32 s1, s2, s1
; GFX11-NEXT: s_sub_i32 s6, 0x3f1, s3
; GFX11-NEXT: s_or_b32 s2, s1, 0x1000
; GFX11-NEXT: v_med3_i32 v0, s6, 0, 13
; GFX11-NEXT: s_addk_i32 s3, 0xfc10
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_lshl_b32 s8, s3, 12
; GFX11-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-NEXT: s_or_b32 s8, s1, s8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s6, s2, s6
; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, s2, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s3, v0
; GFX11-NEXT: s_or_b32 s3, s6, s3
; GFX11-NEXT: s_cmp_lt_i32 s1, 1
; GFX11-NEXT: s_cselect_b32 s3, s3, s8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s6, s3, 7
; GFX11-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s2, s6, s2
; GFX11-NEXT: s_cmp_lt_i32 s3, 1
; GFX11-NEXT: s_cselect_b32 s2, s2, s8
; GFX11-NEXT: s_and_b32 s6, s2, 7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_gt_i32 s6, 5
; GFX11-NEXT: s_cselect_b32 s8, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s6, 3
; GFX11-NEXT: s_cselect_b32 s6, -1, 0
; GFX11-NEXT: s_lshr_b32 s3, s3, 2
; GFX11-NEXT: s_lshr_b32 s2, s2, 2
; GFX11-NEXT: s_or_b32 s6, s6, s8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_lg_u32 s6, 0
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_cmp_lt_i32 s1, 31
; GFX11-NEXT: s_cselect_b32 s3, s3, 0x7c00
; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmpk_eq_i32 s1, 0x40f
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
; GFX11-NEXT: s_addc_u32 s2, s2, 0
; GFX11-NEXT: s_cmp_lt_i32 s3, 31
; GFX11-NEXT: s_cselect_b32 s2, s2, 0x7c00
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, -1, 0
; GFX11-NEXT: s_cmpk_eq_i32 s3, 0x40f
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-NEXT: s_lshr_b32 s1, s7, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_and_b32 s1, s1, 0x8000
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 9, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, 0x7c00, v0
; GFX11-NEXT: v_cndmask_b32_e32 v0, s3, v0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, s1, v0
; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, s0
Expand Down
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