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[InstCombine] Drop exact flag instead of increasing demanded bits #70311

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Merged
merged 1 commit into from
Oct 26, 2023
Merged

[InstCombine] Drop exact flag instead of increasing demanded bits #70311

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21 changes: 8 additions & 13 deletions llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -698,14 +698,11 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,

// Unsigned shift right.
APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));

// If the shift is exact, then it does demand the low bits (and knows that
// they are zero).
if (cast<LShrOperator>(I)->isExact())
DemandedMaskIn.setLowBits(ShiftAmt);

if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1)) {
// exact flag may not longer hold.
I->dropPoisonGeneratingFlags();
return I;
}
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
Known.Zero.lshrInPlace(ShiftAmt);
Known.One.lshrInPlace(ShiftAmt);
Expand Down Expand Up @@ -747,13 +744,11 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
if (DemandedMask.countl_zero() <= ShiftAmt)
DemandedMaskIn.setSignBit();

// If the shift is exact, then it does demand the low bits (and knows that
// they are zero).
if (cast<AShrOperator>(I)->isExact())
DemandedMaskIn.setLowBits(ShiftAmt);

if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1)) {
// exact flag may not longer hold.
I->dropPoisonGeneratingFlags();
return I;
}

assert(!Known.hasConflict() && "Bits known to be one AND zero?");
// Compute the new bits that are at the top now plus sign bits.
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/cast.ll
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Expand Up @@ -1318,7 +1318,7 @@ define i64 @test83(i16 %a, i64 %k) {
define i8 @test84(i32 %a) {
; ALL-LABEL: @test84(
; ALL-NEXT: [[ADD:%.*]] = add i32 [[A:%.*]], 2130706432
; ALL-NEXT: [[SHR:%.*]] = lshr exact i32 [[ADD]], 23
; ALL-NEXT: [[SHR:%.*]] = lshr i32 [[ADD]], 23
; ALL-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR]] to i8
; ALL-NEXT: ret i8 [[TRUNC]]
;
Expand All @@ -1331,7 +1331,7 @@ define i8 @test84(i32 %a) {
define i8 @test85(i32 %a) {
; ALL-LABEL: @test85(
; ALL-NEXT: [[ADD:%.*]] = add i32 [[A:%.*]], 2130706432
; ALL-NEXT: [[SHR:%.*]] = lshr exact i32 [[ADD]], 23
; ALL-NEXT: [[SHR:%.*]] = lshr i32 [[ADD]], 23
; ALL-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR]] to i8
; ALL-NEXT: ret i8 [[TRUNC]]
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/select-2.ll
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Expand Up @@ -45,7 +45,7 @@ define float @t3(float %x, float %y) {

define i8 @ashr_exact_poison_constant_fold(i1 %b, i8 %x) {
; CHECK-LABEL: @ashr_exact_poison_constant_fold(
; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i8 [[X:%.*]], 3
; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[X:%.*]], 3
; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 5
; CHECK-NEXT: ret i8 [[R]]
;
Expand Down
8 changes: 3 additions & 5 deletions llvm/test/Transforms/InstCombine/shift.ll
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Expand Up @@ -2141,9 +2141,8 @@ define i16 @lshr_and_not_demanded(i8 %x) {

define i16 @lshr_exact_and_not_demanded(i8 %x) {
; CHECK-LABEL: @lshr_exact_and_not_demanded(
; CHECK-NEXT: [[Y:%.*]] = and i8 [[X:%.*]], -2
; CHECK-NEXT: [[Y_EXT:%.*]] = sext i8 [[Y]] to i16
; CHECK-NEXT: [[SHR:%.*]] = lshr exact i16 [[Y_EXT]], 1
; CHECK-NEXT: [[Y_EXT:%.*]] = sext i8 [[X:%.*]] to i16
; CHECK-NEXT: [[SHR:%.*]] = lshr i16 [[Y_EXT]], 1
; CHECK-NEXT: ret i16 [[SHR]]
;
%y = and i8 %x, -2
Expand Down Expand Up @@ -2177,8 +2176,7 @@ define i16 @ashr_umax_not_demanded(i16 %x) {

define i16 @ashr_exact_umax_not_demanded(i16 %x) {
; CHECK-LABEL: @ashr_exact_umax_not_demanded(
; CHECK-NEXT: [[Y:%.*]] = call i16 @llvm.umax.i16(i16 [[X:%.*]], i16 1)
; CHECK-NEXT: [[SHR:%.*]] = ashr exact i16 [[Y]], 1
; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[X:%.*]], 1
; CHECK-NEXT: ret i16 [[SHR]]
;
%y = call i16 @llvm.umax.i16(i16 %x, i16 1)
Expand Down