[GISel] Make target's PartMapping, ValueMapping, and BankIDToCopyMapIdx arrays const. #71079
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… arrays const. AMDGPU arrays were already const.
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@llvm/pr-subscribers-backend-m68k @llvm/pr-subscribers-backend-arm Author: Craig Topper (topperc) ChangesAMDGPU arrays were already const. Full diff: https://github.com/llvm/llvm-project/pull/71079.diff 8 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
index 87aef1dfe8cf8f0..b87421e5ee46ae5 100644
--- a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+++ b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
@@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
namespace llvm {
-RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
+const RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
// 0: FPR 16-bit value.
{0, 16, AArch64::FPRRegBank},
@@ -34,7 +34,7 @@ RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
};
// ValueMappings.
-RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
+const RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
/* BreakDown, NumBreakDowns */
// 0: invalid
{nullptr, 0},
@@ -212,7 +212,7 @@ AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
return &ValMappings[ValMappingIdx];
}
-AArch64GenRegisterBankInfo::PartialMappingIdx
+const AArch64GenRegisterBankInfo::PartialMappingIdx
AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
PMI_None, // CCR
PMI_FirstFPR, // FPR
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
index 4d40efb5ac92485..48bd9fbeadb41bc 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
@@ -43,9 +43,9 @@ class AArch64GenRegisterBankInfo : public RegisterBankInfo {
PMI_Min = PMI_FirstFPR,
};
- static RegisterBankInfo::PartialMapping PartMappings[];
- static RegisterBankInfo::ValueMapping ValMappings[];
- static PartialMappingIdx BankIDToCopyMapIdx[];
+ static const RegisterBankInfo::PartialMapping PartMappings[];
+ static const RegisterBankInfo::ValueMapping ValMappings[];
+ static const PartialMappingIdx BankIDToCopyMapIdx[];
enum ValueMappingIdx {
InvalidIdx = 0,
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index f7977941e895109..746a8715df0a652 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -35,7 +35,7 @@ enum PartialMappingIdx {
PMI_Min = PMI_GPR,
};
-RegisterBankInfo::PartialMapping PartMappings[]{
+const RegisterBankInfo::PartialMapping PartMappings[]{
// GPR Partial Mapping
{0, 32, GPRRegBank},
// SPR Partial Mapping
@@ -72,7 +72,7 @@ enum ValueMappingIdx {
DPR3OpsIdx = 7,
};
-RegisterBankInfo::ValueMapping ValueMappings[] = {
+const RegisterBankInfo::ValueMapping ValueMappings[] = {
// invalid
{nullptr, 0},
// 3 ops in GPRs
@@ -89,8 +89,9 @@ RegisterBankInfo::ValueMapping ValueMappings[] = {
{&PartMappings[PMI_DPR - PMI_Min], 1}};
#ifndef NDEBUG
-static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
- RegisterBankInfo::PartialMapping *BreakDown) {
+static bool
+checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
+ const RegisterBankInfo::PartialMapping *BreakDown) {
return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown;
}
diff --git a/llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp b/llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp
index f833eb2d19d46a6..e7e5bb19c3a07e2 100644
--- a/llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp
+++ b/llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp
@@ -33,7 +33,7 @@ enum PartialMappingIdx {
PMI_Min = PMI_GPR,
};
-RegisterBankInfo::PartialMapping PartMappings[]{
+const RegisterBankInfo::PartialMapping PartMappings[]{
// GPR Partial Mapping
{0, 32, GPRRegBank},
};
@@ -43,7 +43,7 @@ enum ValueMappingIdx {
GPR3OpsIdx = 1,
};
-RegisterBankInfo::ValueMapping ValueMappings[] = {
+const RegisterBankInfo::ValueMapping ValueMappings[] = {
// invalid
{nullptr, 0},
// 3 operands in GPRs
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index eeefafbaf633206..b38ca3f09ffbe2f 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -32,7 +32,7 @@ enum PartialMappingIdx {
PMI_Min = PMI_GPR,
};
-RegisterBankInfo::PartialMapping PartMappings[]{
+const RegisterBankInfo::PartialMapping PartMappings[]{
{0, 32, GPRBRegBank},
{0, 32, FPRBRegBank},
{0, 64, FPRBRegBank},
@@ -47,7 +47,7 @@ enum ValueMappingIdx {
MSAIdx = 10
};
-RegisterBankInfo::ValueMapping ValueMappings[] = {
+const RegisterBankInfo::ValueMapping ValueMappings[] = {
// invalid
{nullptr, 0},
// up to 3 operands in GPRs
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
index c2a16c92ba85d01..1477fdca917d75b 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
@@ -37,9 +37,9 @@ class PPCGenRegisterBankInfo : public RegisterBankInfo {
PMI_Min = PMI_GPR32,
};
- static RegisterBankInfo::PartialMapping PartMappings[];
- static RegisterBankInfo::ValueMapping ValMappings[];
- static PartialMappingIdx BankIDToCopyMapIdx[];
+ static const RegisterBankInfo::PartialMapping PartMappings[];
+ static const RegisterBankInfo::ValueMapping ValMappings[];
+ static const PartialMappingIdx BankIDToCopyMapIdx[];
/// Get the pointer to the ValueMapping representing the RegisterBank
/// at \p RBIdx.
diff --git a/llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def b/llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def
index eff4432206e10ad..b42f9247f6917ea 100644
--- a/llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def
@@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===//
namespace llvm {
-RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
+const RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
// 0: GPR 32-bit value.
{0, 32, PPC::GPRRegBank},
@@ -39,7 +39,7 @@ RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
// 3-operands instructions.
// - Last, mappings for cross-register bank moves follow. Since COPY has only
// 2 operands, a mapping consists of 2 entries.
-RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
+const RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
/* BreakDown, NumBreakDowns */
// 0: invalid
{nullptr, 0},
@@ -77,7 +77,7 @@ PPCGenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx) {
return &ValMappings[1 + 3 * ValMappingIdx];
}
-PPCGenRegisterBankInfo::PartialMappingIdx
+const PPCGenRegisterBankInfo::PartialMappingIdx
PPCGenRegisterBankInfo::BankIDToCopyMapIdx[]{
PMI_None,
PMI_FPR64, // FPR
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index f005948d2094445..81d34b5c834019f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -24,7 +24,7 @@
namespace llvm {
namespace RISCV {
-RegisterBankInfo::PartialMapping PartMappings[] = {
+const RegisterBankInfo::PartialMapping PartMappings[] = {
{0, 32, GPRRegBank},
{0, 64, GPRRegBank},
{0, 32, FPRRegBank},
@@ -38,7 +38,7 @@ enum PartialMappingIdx {
PMI_FPR64 = 3,
};
-RegisterBankInfo::ValueMapping ValueMappings[] = {
+const RegisterBankInfo::ValueMapping ValueMappings[] = {
// Invalid value mapping.
{nullptr, 0},
// Maximum 3 GPR operands; 32 bit.
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You can test this locally with the following command:git-clang-format --diff 7d039effc4930be9240446a4241d268a39960e0b e012e48e3dc55605f9161be67bb3d45cab0cf911 -- llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cppView the diff from clang-format here.diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index b38ca3f09..440611c70 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -32,12 +32,10 @@ enum PartialMappingIdx {
PMI_Min = PMI_GPR,
};
-const RegisterBankInfo::PartialMapping PartMappings[]{
- {0, 32, GPRBRegBank},
- {0, 32, FPRBRegBank},
- {0, 64, FPRBRegBank},
- {0, 128, FPRBRegBank}
-};
+const RegisterBankInfo::PartialMapping PartMappings[]{{0, 32, GPRBRegBank},
+ {0, 32, FPRBRegBank},
+ {0, 64, FPRBRegBank},
+ {0, 128, FPRBRegBank}};
enum ValueMappingIdx {
InvalidIdx = 0,
@@ -65,8 +63,7 @@ const RegisterBankInfo::ValueMapping ValueMappings[] = {
// up to 3 operands in FPRs - MSA
{&PartMappings[PMI_MSA - PMI_Min], 1},
{&PartMappings[PMI_MSA - PMI_Min], 1},
- {&PartMappings[PMI_MSA - PMI_Min], 1}
-};
+ {&PartMappings[PMI_MSA - PMI_Min], 1}};
} // end namespace Mips
} // end namespace llvm
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arsenm
approved these changes
Nov 7, 2023
zahiraam
pushed a commit
to zahiraam/llvm-project
that referenced
this pull request
Nov 20, 2023
…dx arrays const. (llvm#71079) AMDGPU arrays were already const.
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AMDGPU arrays were already const.