Skip to content

[InstCombine] When -A + B both have nsw flag, set nsw flag. #72127

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 14, 2023
Merged

[InstCombine] When -A + B both have nsw flag, set nsw flag. #72127

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 5 additions & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1487,7 +1487,11 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
return BinaryOperator::CreateNeg(Builder.CreateAdd(A, B));

// -A + B --> B - A
return BinaryOperator::CreateSub(RHS, A);
auto *Sub = BinaryOperator::CreateSub(RHS, A);
auto *OB0 = dyn_cast<OverflowingBinaryOperator>(LHS);
Sub->setHasNoSignedWrap(I.hasNoSignedWrap() && OB0->hasNoSignedWrap());

return Sub;
}

// A + -B --> A - B
Expand Down
30 changes: 30 additions & 0 deletions llvm/test/Transforms/InstCombine/add.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,36 @@ define i32 @test5(i32 %A, i32 %B) {
ret i32 %D
}

define i32 @test5_both_nsw(i32 %A, i32 %B) {
; CHECK-LABEL: @test5_both_nsw(
; CHECK-NEXT: [[D:%.*]] = sub nsw i32 [[B:%.*]], [[A:%.*]]
; CHECK-NEXT: ret i32 [[D]]
;
%C = sub nsw i32 0, %A
%D = add nsw i32 %C, %B
ret i32 %D
}

define i32 @test5_neg_nsw(i32 %A, i32 %B) {
; CHECK-LABEL: @test5_neg_nsw(
; CHECK-NEXT: [[D:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
; CHECK-NEXT: ret i32 [[D]]
;
%C = sub nsw i32 0, %A
%D = add i32 %C, %B
ret i32 %D
}

define i32 @test5_add_nsw(i32 %A, i32 %B) {
; CHECK-LABEL: @test5_add_nsw(
; CHECK-NEXT: [[D:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
; CHECK-NEXT: ret i32 [[D]]
;
%C = sub i32 0, %A
%D = add nsw i32 %C, %B
ret i32 %D
}

define <2 x i8> @neg_op0_vec_undef_elt(<2 x i8> %a, <2 x i8> %b) {
; CHECK-LABEL: @neg_op0_vec_undef_elt(
; CHECK-NEXT: [[R:%.*]] = sub <2 x i8> [[B:%.*]], [[A:%.*]]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/pr14365.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ define i32 @test1(i32 %a0) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A0:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1431655765
; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[A0]], [[TMP2]]
; CHECK-NEXT: [[TMP3:%.*]] = sub nsw i32 [[A0]], [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = ashr i32 %a0, 1
Expand All @@ -46,7 +46,7 @@ define <4 x i32> @test1_vec(<4 x i32> %a0) {
; CHECK-LABEL: @test1_vec(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765>
; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i32> [[A0]], [[TMP2]]
; CHECK-NEXT: [[TMP3:%.*]] = sub nsw <4 x i32> [[A0]], [[TMP2]]
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
;
%1 = ashr <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
Expand Down