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[AArch64][GISel] Drop custom selectors for ptrauth_* intrinsics #75328

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Merged
merged 1 commit into from
Dec 19, 2023
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[AArch64][GISel] Drop custom selectors for ptrauth_* intrinsics #75328

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62 changes: 0 additions & 62 deletions llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6717,68 +6717,6 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
I.eraseFromParent();
return true;
}
case Intrinsic::ptrauth_sign: {
Register DstReg = I.getOperand(0).getReg();
Register ValReg = I.getOperand(2).getReg();
uint64_t Key = I.getOperand(3).getImm();
Register DiscReg = I.getOperand(4).getReg();
auto DiscVal = getIConstantVRegVal(DiscReg, MRI);
bool IsDiscZero = DiscVal && DiscVal->isZero();

if (Key > AArch64PACKey::LAST)
return false;

unsigned Opcodes[][4] = {
{AArch64::PACIA, AArch64::PACIB, AArch64::PACDA, AArch64::PACDB},
{AArch64::PACIZA, AArch64::PACIZB, AArch64::PACDZA, AArch64::PACDZB}};
unsigned Opcode = Opcodes[IsDiscZero][Key];

auto PAC = MIB.buildInstr(Opcode, {DstReg}, {ValReg});

if (!IsDiscZero) {
PAC.addUse(DiscReg);
RBI.constrainGenericRegister(DiscReg, AArch64::GPR64spRegClass, MRI);
}

RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
I.eraseFromParent();
return true;
}
case Intrinsic::ptrauth_strip: {
Register DstReg = I.getOperand(0).getReg();
Register ValReg = I.getOperand(2).getReg();
uint64_t Key = I.getOperand(3).getImm();

if (Key > AArch64PACKey::LAST)
return false;
unsigned Opcode = getXPACOpcodeForKey((AArch64PACKey::ID)Key);

MIB.buildInstr(Opcode, {DstReg}, {ValReg});

RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
RBI.constrainGenericRegister(ValReg, AArch64::GPR64RegClass, MRI);
I.eraseFromParent();
return true;
}
case Intrinsic::ptrauth_blend: {
MachineFunction &MF = *I.getParent()->getParent();
auto RHS = getIConstantVRegVal(I.getOperand(3).getReg(), MRI);
if (RHS && (RHS->getZExtValue() <= 0xffff)) {
I.setDesc(TII.get(AArch64::MOVKXi));
I.removeOperand(3);
I.removeOperand(1);
MachineInstrBuilder(MF, I)
.addImm(RHS->getZExtValue() & 0xffff)
.addImm(48)
.constrainAllUses(TII, TRI, RBI);
} else {
I.setDesc(TII.get(AArch64::BFMXri));
I.removeOperand(1);
MachineInstrBuilder(MF, I).addImm(16).addImm(15).constrainAllUses(
TII, TRI, RBI);
}
return true;
}
case Intrinsic::frameaddress:
case Intrinsic::returnaddress: {
MachineFunction &MF = *I.getParent()->getParent();
Expand Down