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[AMDGPU][MC] Use normal ELF syntax for section switching #77267

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Jan 9, 2024
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1 change: 0 additions & 1 deletion llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,6 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
InlineAsmEnd = ";#ASMEND";

//===--- Data Emission Directives -------------------------------------===//
SunStyleELFSectionSwitchSyntax = true;
UsesELFSectionDirectiveForBSS = true;

//===--- Global Variable Emission Directives --------------------------===//
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/code-object-v3.ll
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t

; OSABI-AMDHSA-ASM: s_endpgm
; OSABI-AMDHSA-ASM: .section .rodata,#alloc
; OSABI-AMDHSA-ASM: .section .rodata,"a"
; OSABI-AMDHSA-ASM: .p2align 6
; OSABI-AMDHSA-ASM: .amdhsa_kernel fadd
; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_count 6
Expand All @@ -28,7 +28,7 @@
; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t

; OSABI-AMDHSA-ASM: s_endpgm
; OSABI-AMDHSA-ASM: .section .rodata,#alloc
; OSABI-AMDHSA-ASM: .section .rodata,"a"
; OSABI-AMDHSA-ASM: .p2align 6
; OSABI-AMDHSA-ASM: .amdhsa_kernel fsub
; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_count 6
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/hsa-globals.ll
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ define amdgpu_kernel void @test() {
@weak_global = extern_weak addrspace(1) global i32

; ASM: .type linkonce_odr_global_program,@object
; ASM: .section .bss,#alloc,#write
; ASM: .section .bss,"aw"
; ASM: .weak linkonce_odr_global_program
; ASM: linkonce_odr_global_program:
; ASM: .long 0
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
Original file line number Diff line number Diff line change
Expand Up @@ -305,7 +305,7 @@ attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memo

; Table size length number-kernels * number-variables * sizeof(uint16_t)
; GCN: .type llvm.amdgcn.lds.offset.table,@object
; GCN-NEXT: .section .data.rel.ro,#alloc,#write
; GCN-NEXT: .section .data.rel.ro,"aw"
; GCN-NEXT: .p2align 2, 0x0
; GCN-NEXT: llvm.amdgcn.lds.offset.table:
; GCN-NEXT: .long 8
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
Original file line number Diff line number Diff line change
Expand Up @@ -355,7 +355,7 @@ define amdgpu_kernel void @k123() {

; Table size length number-kernels * number-variables * sizeof(uint16_t)
; GCN: .type llvm.amdgcn.lds.offset.table,@object
; GCN-NEXT: .section .data.rel.ro,#alloc,#write
; GCN-NEXT: .section .data.rel.ro,"aw"
; GCN-NEXT: .p2align 4, 0x0
; GCN-NEXT: llvm.amdgcn.lds.offset.table:
; GCN-NEXT: .long 0+4
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ define amdgpu_kernel void @max_alignment_128() #0 {
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
; VI-NEXT: .section .rodata,#alloc
; VI-NEXT: .section .rodata,"a"
; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel max_alignment_128
; VI-NEXT: .amdhsa_group_segment_fixed_size 0
Expand Down Expand Up @@ -60,7 +60,7 @@ define amdgpu_kernel void @max_alignment_128() #0 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .section .rodata,#alloc
; GFX9-NEXT: .section .rodata,"a"
; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel max_alignment_128
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
Expand Down Expand Up @@ -115,7 +115,7 @@ define amdgpu_kernel void @stackrealign_attr() #1 {
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
; VI-NEXT: .section .rodata,#alloc
; VI-NEXT: .section .rodata,"a"
; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel stackrealign_attr
; VI-NEXT: .amdhsa_group_segment_fixed_size 0
Expand Down Expand Up @@ -163,7 +163,7 @@ define amdgpu_kernel void @stackrealign_attr() #1 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .section .rodata,#alloc
; GFX9-NEXT: .section .rodata,"a"
; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel stackrealign_attr
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
Expand Down Expand Up @@ -218,7 +218,7 @@ define amdgpu_kernel void @alignstack_attr() #2 {
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
; VI-NEXT: .section .rodata,#alloc
; VI-NEXT: .section .rodata,"a"
; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel alignstack_attr
; VI-NEXT: .amdhsa_group_segment_fixed_size 0
Expand Down Expand Up @@ -266,7 +266,7 @@ define amdgpu_kernel void @alignstack_attr() #2 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .section .rodata,#alloc
; GFX9-NEXT: .section .rodata,"a"
; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel alignstack_attr
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
Expand Down