Skip to content

[SelectionDAG] Fix isKnownNeverZeroFloat for vectors #78308

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jan 17, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
18 changes: 2 additions & 16 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5233,22 +5233,8 @@ bool SelectionDAG::isKnownNeverZeroFloat(SDValue Op) const {
"Floating point type expected");

// If the value is a constant, we can obviously see if it is a zero or not.
if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
return !C->isZero();

// Return false if we find any zero in a vector.
if (Op->getOpcode() == ISD::BUILD_VECTOR ||
Op->getOpcode() == ISD::SPLAT_VECTOR) {
for (const SDValue &OpVal : Op->op_values()) {
if (OpVal.isUndef())
return false;
if (auto *C = dyn_cast<ConstantFPSDNode>(OpVal))
if (C->isZero())
return false;
}
return true;
}
return false;
return ISD::matchUnaryFpPredicate(
Op, [](ConstantFPSDNode *C) { return !C->isZero(); });
}

bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
Expand Down
35 changes: 25 additions & 10 deletions llvm/test/CodeGen/X86/fminimum-fmaximum.ll
Original file line number Diff line number Diff line change
Expand Up @@ -1328,36 +1328,51 @@ define <4 x float> @test_fmaximum_v4f32_splat(<4 x float> %x, float %y) {
; SSE2-LABEL: test_fmaximum_v4f32_splat:
; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: andps %xmm2, %xmm4
; SSE2-NEXT: orps %xmm3, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: andnps %xmm1, %xmm2
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: maxps %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: cmpunordps %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: andps %xmm2, %xmm3
; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: andnps %xmm0, %xmm2
; SSE2-NEXT: orps %xmm3, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: andps %xmm2, %xmm0
; SSE2-NEXT: andnps %xmm1, %xmm2
; SSE2-NEXT: orps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; AVX1-LABEL: test_fmaximum_v4f32_splat:
; AVX1: # %bb.0:
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
; AVX1-NEXT: vmaxps %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vblendvps %xmm0, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmaxps %xmm2, %xmm0, %xmm1
; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm2
; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX512-LABEL: test_fmaximum_v4f32_splat:
; AVX512: # %bb.0:
; AVX512-NEXT: vbroadcastss %xmm1, %xmm1
; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm1
; AVX512-NEXT: vblendvps %xmm0, %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vblendvps %xmm0, %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmaxps %xmm2, %xmm0, %xmm1
; AVX512-NEXT: vcmpunordps %xmm0, %xmm0, %xmm2
; AVX512-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX512-NEXT: retq
;
; X86-LABEL: test_fmaximum_v4f32_splat:
; X86: # %bb.0:
; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1
; X86-NEXT: vmaxps %xmm1, %xmm0, %xmm1
; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm0, %xmm2
; X86-NEXT: vblendvps %xmm0, %xmm0, %xmm1, %xmm0
; X86-NEXT: vmaxps %xmm2, %xmm0, %xmm1
; X86-NEXT: vcmpunordps %xmm0, %xmm0, %xmm2
; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; X86-NEXT: retl
Expand Down