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[AMDGPU] Rework architected SGPRs implementation #79001

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12 changes: 9 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
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Expand Up @@ -100,13 +100,19 @@ AMDGPUFunctionArgInfo::getPreloadedValue(
&AMDGPU::SGPR_64RegClass,
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
return std::tuple(ArchitectedWorkGroupIDX ? &ArchitectedWorkGroupIDX
: WorkGroupIDX ? &WorkGroupIDX
: nullptr,
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
return std::tuple(ArchitectedWorkGroupIDY ? &ArchitectedWorkGroupIDY
: WorkGroupIDY ? &WorkGroupIDY
: nullptr,
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
return std::tuple(ArchitectedWorkGroupIDZ ? &ArchitectedWorkGroupIDZ
: WorkGroupIDZ ? &WorkGroupIDZ
: nullptr,
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
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Expand Up @@ -143,6 +143,11 @@ struct AMDGPUFunctionArgInfo {
ArgDescriptor WorkGroupInfo;
ArgDescriptor PrivateSegmentWaveByteOffset;

// System TTMPs.
ArgDescriptor ArchitectedWorkGroupIDX;
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I don't think these really need to be tracked in ArgumentUsageInfo; they aren't arguments anymore

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OK. I started again from scratch: #79120

ArgDescriptor ArchitectedWorkGroupIDY;
ArgDescriptor ArchitectedWorkGroupIDZ;

// Pointer with offset from kernargsegmentptr to where special ABI arguments
// are passed to callable functions.
ArgDescriptor ImplicitArgPtr;
Expand Down
30 changes: 13 additions & 17 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -2496,28 +2496,27 @@ void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
}
}

if (Info.hasWorkGroupIDX()) {
Register Reg = Info.addWorkGroupIDX(HasArchitectedSGPRs);
if (!HasArchitectedSGPRs)
if (!HasArchitectedSGPRs) {
if (Info.hasWorkGroupIDX()) {
Register Reg = Info.addWorkGroupIDX();
MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);

CCInfo.AllocateReg(Reg);
}
CCInfo.AllocateReg(Reg);
}

if (Info.hasWorkGroupIDY()) {
Register Reg = Info.addWorkGroupIDY(HasArchitectedSGPRs);
if (!HasArchitectedSGPRs)
if (Info.hasWorkGroupIDY()) {
Register Reg = Info.addWorkGroupIDY();
MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);

CCInfo.AllocateReg(Reg);
}
CCInfo.AllocateReg(Reg);
}

if (Info.hasWorkGroupIDZ()) {
Register Reg = Info.addWorkGroupIDZ(HasArchitectedSGPRs);
if (!HasArchitectedSGPRs)
if (Info.hasWorkGroupIDZ()) {
Register Reg = Info.addWorkGroupIDZ();
MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);

CCInfo.AllocateReg(Reg);
CCInfo.AllocateReg(Reg);
}
}

if (Info.hasWorkGroupInfo()) {
Expand Down Expand Up @@ -2722,9 +2721,6 @@ SDValue SITargetLowering::LowerFormalArguments(
(void)UserSGPRInfo;
if (!Subtarget->enableFlatScratch())
assert(!UserSGPRInfo.hasFlatScratchInit());
if (CallConv != CallingConv::AMDGPU_CS || !Subtarget->hasArchitectedSGPRs())
assert(!Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ());
}

if (CallConv == CallingConv::AMDGPU_PS) {
Expand Down
13 changes: 11 additions & 2 deletions llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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Expand Up @@ -107,8 +107,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
}

if (!AMDGPU::isGraphics(CC) ||
(CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) {
if (!AMDGPU::isGraphics(CC) || CC == CallingConv::AMDGPU_CS ||
ST.hasArchitectedSGPRs()) {
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This change looks redundant as this patch always allocate the TTMP* for subtargets with architectedSGPR enabled.
This was initially added with 2171f04.
You can revert this check to just have only !AMDGPU::isGraphics(CC)

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But I need WorkGroupIDZ to be set correctly when architected SGPRs are enabled. It is used below, line 177.

if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
WorkGroupIDX = true;

Expand Down Expand Up @@ -169,6 +169,15 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
VGPRForAGPRCopy =
AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
}

if (STI->hasArchitectedSGPRs()) {
ArgInfo.ArchitectedWorkGroupIDX =
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I think it's OK for the lowering to directly consume the hardcoded register numbers

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You mean not go via these ArgDescriptors? I'm only using them because they handle the shifting and masking.

ArgDescriptor::createRegister(AMDGPU::TTMP9);
ArgInfo.ArchitectedWorkGroupIDY = ArgDescriptor::createRegister(
AMDGPU::TTMP7, WorkGroupIDZ ? 0xFFFFu : ~0u);
ArgInfo.ArchitectedWorkGroupIDZ =
ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u);
}
}

MachineFunctionInfo *SIMachineFunctionInfo::clone(
Expand Down
30 changes: 11 additions & 19 deletions llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
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Expand Up @@ -744,34 +744,26 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
}

// Add system SGPRs.
Register addWorkGroupIDX(bool HasArchitectedSGPRs) {
Register Reg =
HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP9 : getNextSystemSGPR();
Register addWorkGroupIDX() {
Register Reg = getNextSystemSGPR();
ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(Reg);
if (!HasArchitectedSGPRs)
NumSystemSGPRs += 1;
NumSystemSGPRs += 1;

return ArgInfo.WorkGroupIDX.getRegister();
}

Register addWorkGroupIDY(bool HasArchitectedSGPRs) {
Register Reg =
HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
unsigned Mask = HasArchitectedSGPRs && hasWorkGroupIDZ() ? 0xffff : ~0u;
ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg, Mask);
if (!HasArchitectedSGPRs)
NumSystemSGPRs += 1;
Register addWorkGroupIDY() {
Register Reg = getNextSystemSGPR();
ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg);
NumSystemSGPRs += 1;

return ArgInfo.WorkGroupIDY.getRegister();
}

Register addWorkGroupIDZ(bool HasArchitectedSGPRs) {
Register Reg =
HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
unsigned Mask = HasArchitectedSGPRs ? 0xffff << 16 : ~0u;
ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(Reg, Mask);
if (!HasArchitectedSGPRs)
NumSystemSGPRs += 1;
Register addWorkGroupIDZ() {
Register Reg = getNextSystemSGPR();
ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(Reg);
NumSystemSGPRs += 1;

return ArgInfo.WorkGroupIDZ.getRegister();
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
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Expand Up @@ -147,7 +147,7 @@ define amdgpu_cs void @test_buffer_load_sgpr_plus_imm_offset_nuw(<4 x i32> inreg
; GISEL-DAG: %[[BASE3:.*]]:sreg_32 = COPY $sgpr3
; GISEL-DAG: %[[OFFSET:.*]]:sreg_32 = COPY $sgpr4
; GISEL-DAG: %[[BASE:.*]]:sgpr_128 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1, %[[BASE2]], %subreg.sub2, %[[BASE3]], %subreg.sub3
; GISEL-DAG: %[[ADD:.*]]:sreg_32 = nsw S_ADD_I32 %1, %10, implicit-def dead $scc
; GISEL-DAG: %[[ADD:.*]]:sreg_32 = nsw S_ADD_I32 %1, %13, implicit-def dead $scc
; GISEL: S_BUFFER_LOAD_DWORD_SGPR_IMM %[[BASE]], %[[ADD]], 0,
define amdgpu_cs void @test_buffer_load_sgpr_plus_imm_offset_nsw(<4 x i32> inreg %base, i32 inreg %i, ptr addrspace(1) inreg %out) #0 {
%off = add nsw i32 %i, 77
Expand All @@ -171,7 +171,7 @@ define amdgpu_cs void @test_buffer_load_sgpr_plus_imm_offset_nsw(<4 x i32> inreg
; GISEL-DAG: %[[BASE3:.*]]:sreg_32 = COPY $sgpr3
; GISEL-DAG: %[[OFFSET:.*]]:sreg_32 = COPY $sgpr4
; GISEL-DAG: %[[BASE:.*]]:sgpr_128 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1, %[[BASE2]], %subreg.sub2, %[[BASE3]], %subreg.sub3
; GISEL-DAG: %[[ADD:.*]]:sreg_32 = S_ADD_I32 %1, %10, implicit-def dead $scc
; GISEL-DAG: %[[ADD:.*]]:sreg_32 = S_ADD_I32 %1, %13, implicit-def dead $scc
; GISEL: S_BUFFER_LOAD_DWORD_SGPR_IMM %[[BASE]], %[[ADD]], 0,
define amdgpu_cs void @test_buffer_load_sgpr_plus_imm_offset_noflags(<4 x i32> inreg %base, i32 inreg %i, ptr addrspace(1) inreg %out) #0 {
%off = add i32 %i, 77
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
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Expand Up @@ -16,8 +16,8 @@ define amdgpu_ps i32 @test_ps() #1 {
}

; GCN-LABEL: {{^}}test_cs:
; GCN: s_mov_b64 s[4:5], s[0:1]
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], 0 offset:4
; GCN: s_mov_b64 s[8:9], s[0:1]
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[8:11], 0 offset:4
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Is this expected?

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No, I guess I've broken something.

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The following change? It now enables workgroup IDs for AMDGPU_CS always.
SIMachineFunctionInfo.cpp:110

  • if (!AMDGPU::isGraphics(CC) ||
  • (CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) {
  • if (!AMDGPU::isGraphics(CC) || CC == CallingConv::AMDGPU_CS ||
  • ST.hasArchitectedSGPRs()) {

; GCN: s_load_dword s0, s[0:1], 0x0
define amdgpu_cs i32 @test_cs() #1 {
%alloca = alloca i32, addrspace(5)
Expand Down
149 changes: 149 additions & 0 deletions llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
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@@ -0,0 +1,149 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs --verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel --verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-GISEL %s

define amdgpu_kernel void @workgroup_ids_kernel() {
; GFX9-SDAG-LABEL: workgroup_ids_kernel:
; GFX9-SDAG: ; %bb.0: ; %.entry
; GFX9-SDAG-NEXT: s_lshr_b32 s2, ttmp7, 16
; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s2
; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; GFX9-SDAG-NEXT: s_endpgm
;
; GFX9-GISEL-LABEL: workgroup_ids_kernel:
; GFX9-GISEL: ; %bb.0: ; %.entry
; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9
; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff
; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
.entry:
%idx = call i32 @llvm.amdgcn.workgroup.id.x()
%idy = call i32 @llvm.amdgcn.workgroup.id.y()
%idz = call i32 @llvm.amdgcn.workgroup.id.z()
%ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0
%ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1
%ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
ret void
}

define amdgpu_kernel void @caller() {
; GFX9-SDAG-LABEL: caller:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX9-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX9-SDAG-NEXT: s_mov_b32 s38, -1
; GFX9-SDAG-NEXT: s_mov_b32 s39, 0xe00000
; GFX9-SDAG-NEXT: s_add_u32 s36, s36, s8
; GFX9-SDAG-NEXT: s_addc_u32 s37, s37, 0
; GFX9-SDAG-NEXT: s_add_u32 s8, s4, 36
; GFX9-SDAG-NEXT: s_addc_u32 s9, s5, 0
; GFX9-SDAG-NEXT: s_getpc_b64 s[4:5]
; GFX9-SDAG-NEXT: s_add_u32 s4, s4, callee@gotpcrel32@lo+4
; GFX9-SDAG-NEXT: s_addc_u32 s5, s5, callee@gotpcrel32@hi+12
; GFX9-SDAG-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x0
; GFX9-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-SDAG-NEXT: s_mov_b32 s12, ttmp9
; GFX9-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
; GFX9-SDAG-NEXT: s_mov_b32 s32, 0
; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT: s_swappc_b64 s[30:31], s[14:15]
; GFX9-SDAG-NEXT: s_endpgm
;
; GFX9-GISEL-LABEL: caller:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX9-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX9-GISEL-NEXT: s_mov_b32 s38, -1
; GFX9-GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GFX9-GISEL-NEXT: s_add_u32 s36, s36, s8
; GFX9-GISEL-NEXT: s_addc_u32 s37, s37, 0
; GFX9-GISEL-NEXT: s_add_u32 s8, s4, 36
; GFX9-GISEL-NEXT: s_addc_u32 s9, s5, 0
; GFX9-GISEL-NEXT: s_mov_b64 s[14:15], s[0:1]
; GFX9-GISEL-NEXT: s_getpc_b64 s[0:1]
; GFX9-GISEL-NEXT: s_add_u32 s0, s0, callee@gotpcrel32@lo+4
; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, callee@gotpcrel32@hi+12
; GFX9-GISEL-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x0
; GFX9-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-GISEL-NEXT: s_mov_b32 s12, ttmp9
; GFX9-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9
; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], s[14:15]
; GFX9-GISEL-NEXT: s_mov_b32 s32, 0
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX9-GISEL-NEXT: s_endpgm
%idx = call i32 @llvm.amdgcn.workgroup.id.x()
call void @callee(i32 %idx) #0
ret void
}

declare void @callee(i32) #0

define void @workgroup_ids_device_func(ptr addrspace(1) %outx, ptr addrspace(1) %outy, ptr addrspace(1) %outz) {
; GFX9-SDAG-LABEL: workgroup_ids_device_func:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, ttmp9
; GFX9-SDAG-NEXT: s_and_b32 s4, ttmp7, 0xffff
; GFX9-SDAG-NEXT: global_store_dword v[0:1], v6, off
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4
; GFX9-SDAG-NEXT: s_lshr_b32 s4, ttmp7, 16
; GFX9-SDAG-NEXT: global_store_dword v[2:3], v0, off
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4
; GFX9-SDAG-NEXT: global_store_dword v[4:5], v0, off
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: workgroup_ids_device_func:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: s_and_b32 s6, ttmp7, 0xffff
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, ttmp9
; GFX9-GISEL-NEXT: s_lshr_b32 s5, ttmp7, 16
; GFX9-GISEL-NEXT: global_store_dword v[0:1], v6, off
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX9-GISEL-NEXT: global_store_dword v[2:3], v0, off
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s5
; GFX9-GISEL-NEXT: global_store_dword v[4:5], v0, off
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%id.x = call i32 @llvm.amdgcn.workgroup.id.x()
%id.y = call i32 @llvm.amdgcn.workgroup.id.y()
%id.z = call i32 @llvm.amdgcn.workgroup.id.z()
store volatile i32 %id.x, ptr addrspace(1) %outx
store volatile i32 %id.y, ptr addrspace(1) %outy
store volatile i32 %id.z, ptr addrspace(1) %outz
ret void
}

declare i32 @llvm.amdgcn.workgroup.id.x()
declare i32 @llvm.amdgcn.workgroup.id.y()
declare i32 @llvm.amdgcn.workgroup.id.z()
declare void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32>, ptr addrspace(8), i32, i32, i32 immarg)

attributes #0 = { nounwind "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" }
41 changes: 41 additions & 0 deletions .../AMDGPU/lower-work-group-id-intrinsics.ll → ...GPU/lower-work-group-id-intrinsics-pal.ll
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Expand Up @@ -75,6 +75,47 @@ define amdgpu_cs void @caller() {

declare amdgpu_gfx void @callee(i32)

define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace(1) %outy, ptr addrspace(1) %outz) {
; GFX9-SDAG-LABEL: workgroup_ids_gfx:
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, ttmp9
; GFX9-SDAG-NEXT: s_and_b32 s34, ttmp7, 0xffff
; GFX9-SDAG-NEXT: global_store_dword v[0:1], v6, off
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s34
; GFX9-SDAG-NEXT: s_lshr_b32 s34, ttmp7, 16
; GFX9-SDAG-NEXT: global_store_dword v[2:3], v0, off
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s34
; GFX9-SDAG-NEXT: global_store_dword v[4:5], v0, off
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: workgroup_ids_gfx:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: s_and_b32 s36, ttmp7, 0xffff
; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, ttmp9
; GFX9-GISEL-NEXT: s_lshr_b32 s35, ttmp7, 16
; GFX9-GISEL-NEXT: global_store_dword v[0:1], v6, off
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s36
; GFX9-GISEL-NEXT: global_store_dword v[2:3], v0, off
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s35
; GFX9-GISEL-NEXT: global_store_dword v[4:5], v0, off
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%id.x = call i32 @llvm.amdgcn.workgroup.id.x()
%id.y = call i32 @llvm.amdgcn.workgroup.id.y()
%id.z = call i32 @llvm.amdgcn.workgroup.id.z()
store volatile i32 %id.x, ptr addrspace(1) %outx
store volatile i32 %id.y, ptr addrspace(1) %outy
store volatile i32 %id.z, ptr addrspace(1) %outz
ret void
}

declare i32 @llvm.amdgcn.workgroup.id.x()
declare i32 @llvm.amdgcn.workgroup.id.y()
declare i32 @llvm.amdgcn.workgroup.id.z()
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