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[RISCV] Add srmcfg CSR from Ssqosid extension. #79914

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Feb 1, 2024
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[RISCV] Add srmcfg CSR from Ssqosid extension. #79914

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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSystemOperands.td
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Original file line number Diff line number Diff line change
Expand Up @@ -132,6 +132,11 @@ def : SysReg<"sip", 0x144>;
let DeprecatedName = "sptbr" in
def : SysReg<"satp", 0x180>;

//===----------------------------------------------------------------------===//
// Quality-of-Service(QoS) Identifiers (Ssqosid)
//===----------------------------------------------------------------------===//
def : SysReg<"srmcfg", 0x181>;
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Two questions.

  1. Where in the specification is the register number mentioned? I didn't find it with some quick searching.

  2. Do we need to do anything special to worry about sysregs of different sizes? This one is SXLEN-bit for instance, and I don't see that obviously being reflected here.

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  1. End of the paragraph at the beginning of Chapter 2.

The srmcfg register is an SXLEN-bit read/write register used to configure a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). Both RCID and MCID are WARL fields. The register is
formatted as shown in Figure 1 when SXLEN=64 and Figure 2 when SXLEN=32. The CSR number is
0x181.

  1. I don't think so. The only thing I know about is registers that have a high register for RV32.

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On the register number, I swear I grepped for those words. Thanks.


//===----------------------------------------------------------------------===//
// Debug/Trace Registers
//===----------------------------------------------------------------------===//
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18 changes: 18 additions & 0 deletions llvm/test/MC/RISCV/supervisor-csr-names.s
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Expand Up @@ -196,6 +196,24 @@ csrrs t1, satp, zero
# uimm12
csrrs t2, 0x180, zero

#########################################
# Quality-of-Service(QoS) Identifiers
#########################################

# srmcfg
# name
# CHECK-INST: csrrs t1, srmcfg, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x18]
# CHECK-INST-ALIAS: csrr t1, srmcfg
# uimm12
# CHECK-INST: csrrs t2, srmcfg, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x18]
# CHECK-INST-ALIAS: csrr t2, srmcfg
# name
csrrs t1, srmcfg, zero
# uimm12
csrrs t2, 0x181, zero

#########################################
# Debug/Trace Registers
#########################################
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