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[GISEL][RISCV] IRTranslator for scalable vector load #80006

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Merged
merged 9 commits into from
Mar 20, 2024
Merged

[GISEL][RISCV] IRTranslator for scalable vector load #80006

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ca41da4
GISel support is in progress for G_LOAD
jiahanxie353 Jan 15, 2024
5fb8065
change the type of StoreSize to be TypeSize
jiahanxie353 Jan 30, 2024
ba22af9
simple test case for scalable vector load
jiahanxie353 Jan 30, 2024
c39ba13
add test check for this simplest test case
jiahanxie353 Jan 30, 2024
20f55a5
have comprehensive test for all vector types and both rv32/64
jiahanxie353 Jan 30, 2024
5b7d826
update test cases
jiahanxie353 Feb 28, 2024
27ccfbe
add align argument
jiahanxie353 Feb 28, 2024
0c407ee
align can be smaller/equal/larger than individual element size and sm…
jiahanxie353 Mar 5, 2024
16dfb7b
load a vector of pointers
jiahanxie353 Mar 5, 2024
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5 changes: 2 additions & 3 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1363,9 +1363,8 @@ static bool isSwiftError(const Value *V) {

bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
const LoadInst &LI = cast<LoadInst>(U);

unsigned StoreSize = DL->getTypeStoreSize(LI.getType());
if (StoreSize == 0)
TypeSize StoreSize = DL->getTypeStoreSize(LI.getType());
if (StoreSize.isZero())
return true;

ArrayRef<Register> Regs = getOrCreateVRegs(LI);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -20909,7 +20909,7 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
if (Op == Instruction::Add || Op == Instruction::Sub ||
Op == Instruction::And || Op == Instruction::Or ||
Op == Instruction::Xor || Op == Instruction::InsertElement ||
Op == Instruction::Xor || Op == Instruction::ShuffleVector)
Op == Instruction::ShuffleVector || Op == Instruction::Load)
return false;

if (Inst.getType()->isScalableTy())
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