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[GISEL] More accounting for scalable vectors when operating on LLTs #80372

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Merged
merged 1 commit into from
Feb 2, 2024
Merged

[GISEL] More accounting for scalable vectors when operating on LLTs #80372

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13 changes: 7 additions & 6 deletions llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -412,7 +412,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
// size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
// have the same elt type, i.e. v4s32.
// TODO: Extend this coersion to element multiples other than just 2.
if (PartLLT.getSizeInBits() > LLTy.getSizeInBits() &&
if (TypeSize::isKnownGT(PartLLT.getSizeInBits(), LLTy.getSizeInBits()) &&
PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
Regs.size() == 1) {
LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
Expand Down Expand Up @@ -529,7 +529,7 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
// We could just insert a regular copy, but this is unreachable at the moment.
assert(SrcTy != PartTy && "identical part types shouldn't reach here");

const unsigned PartSize = PartTy.getSizeInBits();
const TypeSize PartSize = PartTy.getSizeInBits();

if (PartTy.isVector() == SrcTy.isVector() &&
PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
Expand All @@ -539,7 +539,7 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
}

if (SrcTy.isVector() && !PartTy.isVector() &&
PartSize > SrcTy.getElementType().getSizeInBits()) {
TypeSize::isKnownGT(PartSize, SrcTy.getElementType().getSizeInBits())) {
// Vector was scalarized, and the elements extended.
auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
for (int i = 0, e = DstRegs.size(); i != e; ++i)
Expand All @@ -548,9 +548,10 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
}

if (SrcTy.isVector() && PartTy.isVector() &&
PartTy.getScalarSizeInBits() == SrcTy.getScalarSizeInBits() &&
SrcTy.getNumElements() < PartTy.getNumElements()) {
// A coercion like: v2f32 -> v4f32.
PartTy.getSizeInBits() == SrcTy.getSizeInBits() &&
ElementCount::isKnownLT(SrcTy.getElementCount(),
PartTy.getElementCount())) {
// A coercion like: v2f32 -> v4f32 or nxv2f32 -> nxv4f32
Register DstReg = DstRegs.front();
B.buildPadVectorWithUndefElements(DstReg, SrcReg);
return;
Expand Down
10 changes: 8 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/Utils.cpp
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Expand Up @@ -1117,12 +1117,18 @@ LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
}

LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {

if ((OrigTy.isScalableVector() && TargetTy.isFixedVector()) ||
(OrigTy.isFixedVector() && TargetTy.isScalableVector()))
llvm_unreachable(
"getCoverTy not implemented between fixed and scalable vectors.");

if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
(OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
return getLCMType(OrigTy, TargetTy);

unsigned OrigTyNumElts = OrigTy.getNumElements();
unsigned TargetTyNumElts = TargetTy.getNumElements();
unsigned OrigTyNumElts = OrigTy.getElementCount().getKnownMinValue();
unsigned TargetTyNumElts = TargetTy.getElementCount().getKnownMinValue();
if (OrigTyNumElts % TargetTyNumElts == 0)
return OrigTy;

Expand Down
7 changes: 4 additions & 3 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Expand Up @@ -1400,7 +1400,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
if (DstTy.isVector()) {
// This case is the converse of G_CONCAT_VECTORS.
if (!SrcTy.isVector() || SrcTy.getScalarType() != DstTy.getScalarType() ||
SrcTy.getNumElements() != NumDsts * DstTy.getNumElements())
SrcTy.isScalableVector() != DstTy.isScalableVector() ||
SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
report("G_UNMERGE_VALUES source operand does not match vector "
"destination operands",
MI);
Expand Down Expand Up @@ -1477,8 +1478,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
if (DstTy.getNumElements() !=
SrcTy.getNumElements() * (MI->getNumOperands() - 1))
if (DstTy.getElementCount() !=
SrcTy.getElementCount() * (MI->getNumOperands() - 1))
report("G_CONCAT_VECTOR num dest and source elements should match", MI);
break;
}
Expand Down