Skip to content

[AMDGPU][MC] Fix printing vcc(_lo) twice for VOPC DPP instrucitons #81158

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Feb 12, 2024
Merged

[AMDGPU][MC] Fix printing vcc(_lo) twice for VOPC DPP instrucitons #81158

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
b3893db
Use full asm with encoding in check lines
mbrkusanin Feb 8, 2024
3cc9650
Fix printing vcc(_lo) twice for VOPC DPP instrucitons
mbrkusanin Feb 8, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -709,6 +709,7 @@ bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
unsigned OpNo) const {
return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
(Desc.TSFlags & SIInstrFlags::VOPC) &&
!isVOPCAsmOnly(Desc.getOpcode()) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
}
Expand All @@ -725,7 +726,7 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
// printOperandAndIntInputMods will be called instead
if ((OpNo == 0 ||
(OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
(Desc.TSFlags & SIInstrFlags::VOPC) &&
(Desc.TSFlags & SIInstrFlags::VOPC) && !isVOPCAsmOnly(Desc.getOpcode()) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
printDefaultVccOperand(true, STI, O);
Expand Down
16 changes: 16 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -342,6 +342,14 @@ struct VOPC64DPPInfo {
uint16_t Opcode;
};

struct VOPCDPPAsmOnlyInfo {
uint16_t Opcode;
};

struct VOP3CDPPAsmOnlyInfo {
uint16_t Opcode;
};

struct VOPDComponentInfo {
uint16_t BaseVOP;
uint16_t VOPDOp;
Expand Down Expand Up @@ -376,6 +384,10 @@ struct VOPTrue16Info {
#define GET_VOPC64DPPTable_IMPL
#define GET_VOPC64DPP8Table_DECL
#define GET_VOPC64DPP8Table_IMPL
#define GET_VOPCAsmOnlyInfoTable_DECL
#define GET_VOPCAsmOnlyInfoTable_IMPL
#define GET_VOP3CAsmOnlyInfoTable_DECL
#define GET_VOP3CAsmOnlyInfoTable_IMPL
#define GET_VOPDComponentTable_DECL
#define GET_VOPDComponentTable_IMPL
#define GET_VOPDPairs_DECL
Expand Down Expand Up @@ -477,6 +489,10 @@ bool isVOPC64DPP(unsigned Opc) {
return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
}

bool isVOPCAsmOnly(unsigned Opc) {
return isVOPCAsmOnlyOpcodeHelper(Opc) || isVOP3CAsmOnlyOpcodeHelper(Opc);
}

bool getMAIIsDGEMM(unsigned Opc) {
const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
return Info ? Info->is_dgemm : false;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -489,6 +489,9 @@ bool getVOP3IsSingle(unsigned Opc);
LLVM_READONLY
bool isVOPC64DPP(unsigned Opc);

LLVM_READONLY
bool isVOPCAsmOnly(unsigned Opc);

/// Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY
bool getMAIIsDGEMM(unsigned Opc);
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/VOPCInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1165,6 +1165,8 @@ class VOPC_DPPe_Common<bits<8> op> : Enc64 {
class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
: VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>,
VOPC_DPPe_Common<op> {
Instruction Opcode = !cast<Instruction>(NAME);

bits<2> src0_modifiers;
bits<8> src0;
bits<2> src1_modifiers;
Expand Down Expand Up @@ -1194,6 +1196,8 @@ class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
: VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>,
VOPC_DPPe_Common<op> {
Instruction Opcode = !cast<Instruction>(NAME);

bits<8> src0;
bits<24> dpp8;
bits<9> fi;
Expand Down
13 changes: 13 additions & 0 deletions llvm/lib/Target/AMDGPU/VOPInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1669,6 +1669,19 @@ class VOPC64Table <string Format> : GenericTable {
def VOPC64DPPTable : VOPC64Table<"DPP">;
def VOPC64DPP8Table : VOPC64Table<"DPP8">;

class AsmOnlyInfoTable <string Format, string Class>: GenericTable {
let FilterClass = Class;
let FilterClassField = "isAsmParserOnly";
let CppTypeName = Format # "DPPAsmOnlyInfo";
let Fields = ["Opcode"];

let PrimaryKey = ["Opcode"];
let PrimaryKeyName = "is" # Format # "AsmOnlyOpcodeHelper";
}

def VOPCAsmOnlyInfoTable : AsmOnlyInfoTable <"VOPC", "VOPC_DPPe_Common">;
def VOP3CAsmOnlyInfoTable : AsmOnlyInfoTable <"VOP3C", "VOP3_DPPe_Common_Base">;

def VOPTrue16Table : GenericTable {
let FilterClass = "VOP_Pseudo";
let CppTypeName = "VOPTrue16Info";
Expand Down
Loading