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[AArch64] Initial Ampere1B scheduling model #81341

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Merged
merged 3 commits into from
Feb 14, 2024
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[AArch64] Initial Ampere1B scheduling model #81341

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323c588
[AArch64] Initial Ampere1B scheduling model
ptomsich Feb 9, 2024
7b82c3c
fixup! [AArch64] Initial Ampere1B scheduling model
ptomsich Feb 14, 2024
03f4c85
fixup! [AArch64] Initial Ampere1B scheduling model
ptomsich Feb 14, 2024
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5 changes: 3 additions & 2 deletions llvm/lib/Target/AArch64/AArch64.td
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Original file line number Diff line number Diff line change
Expand Up @@ -837,6 +837,7 @@ include "AArch64SchedA64FX.td"
include "AArch64SchedThunderX3T110.td"
include "AArch64SchedTSV110.td"
include "AArch64SchedAmpere1.td"
include "AArch64SchedAmpere1B.td"
include "AArch64SchedNeoverseN1.td"
include "AArch64SchedNeoverseN2.td"
include "AArch64SchedNeoverseV1.td"
Expand Down Expand Up @@ -1555,7 +1556,7 @@ def ProcessorFeatures {
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES, FeatureCSSC,
FeatureWFxT];
FeatureWFxT, FeatureFullFP16];

// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not
Expand Down Expand Up @@ -1723,7 +1724,7 @@ def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
[TuneAmpere1A]>;

def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B,
[TuneAmpere1B]>;

//===----------------------------------------------------------------------===//
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedA53.td
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Expand Up @@ -29,7 +29,7 @@ def CortexA53Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
[HasMTE]);
[HasMTE, HasCSSC]);
}


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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedA57.td
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Expand Up @@ -34,7 +34,7 @@ def CortexA57Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
[HasMTE]);
[HasMTE, HasCSSC]);
}

//===----------------------------------------------------------------------===//
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64SchedA64FX.td
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Expand Up @@ -22,7 +22,8 @@ def A64FXModel : SchedMachineModel {

list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
[HasMTE, HasMatMulInt8, HasBF16,
HasPAuth, HasPAuthLR, HasCPA]);
HasPAuth, HasPAuthLR, HasCPA,
HasCSSC]);
let FullInstRWOverlapCheck = 0;
}

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