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[ConstraintElim] Decompose sext-like insts for signed predicates #82344

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Feb 22, 2024
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[ConstraintElim] Decompose sext-like insts for signed predicates #82344

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5c3ddf9
[ConstraintElim] Fix pre-commit tests in #82357. NFC.
dtcxzyw Feb 22, 2024
d3a709e
[ConstraintElim] Decompose sext-like insts for signed predicates
dtcxzyw Feb 22, 2024
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13 changes: 11 additions & 2 deletions llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -499,6 +499,8 @@ static Decomposition decompose(Value *V,
if (!Ty->isIntegerTy() || Ty->getIntegerBitWidth() > 64)
return V;

bool IsKnownNonNegative = false;

// Decompose \p V used with a signed predicate.
if (IsSigned) {
if (auto *CI = dyn_cast<ConstantInt>(V)) {
Expand All @@ -507,6 +509,14 @@ static Decomposition decompose(Value *V,
}
Value *Op0;
Value *Op1;

if (match(V, m_SExt(m_Value(Op0))))
V = Op0;
else if (match(V, m_NNegZExt(m_Value(Op0)))) {
V = Op0;
IsKnownNonNegative = true;
}

if (match(V, m_NSWAdd(m_Value(Op0), m_Value(Op1))))
return MergeResults(Op0, Op1, IsSigned);

Expand All @@ -529,7 +539,7 @@ static Decomposition decompose(Value *V,
}
}

return V;
return {V, IsKnownNonNegative};
}

if (auto *CI = dyn_cast<ConstantInt>(V)) {
Expand All @@ -539,7 +549,6 @@ static Decomposition decompose(Value *V,
}

Value *Op0;
bool IsKnownNonNegative = false;
if (match(V, m_ZExt(m_Value(Op0)))) {
IsKnownNonNegative = true;
V = Op0;
Expand Down
9 changes: 3 additions & 6 deletions llvm/test/Transforms/ConstraintElimination/minmax.ll
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Expand Up @@ -611,8 +611,7 @@ define i64 @pr82271(i32 %a, i32 %b){
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
; CHECK-NEXT: ret i64 [[SMAX]]
; CHECK-NEXT: ret i64 [[SB]]
; CHECK: else:
; CHECK-NEXT: ret i64 0
;
Expand Down Expand Up @@ -641,8 +640,7 @@ define i64 @pr82271_sext_zext_nneg(i32 %a, i32 %b){
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
; CHECK-NEXT: ret i64 [[SMAX]]
; CHECK-NEXT: ret i64 [[SB]]
; CHECK: else:
; CHECK-NEXT: ret i64 0
;
Expand Down Expand Up @@ -671,8 +669,7 @@ define i64 @pr82271_zext_nneg(i32 %a, i32 %b){
; CHECK-NEXT: [[SA:%.*]] = zext nneg i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
; CHECK-NEXT: ret i64 [[SMAX]]
; CHECK-NEXT: ret i64 [[SB]]
; CHECK: else:
; CHECK-NEXT: ret i64 0
;
Expand Down
84 changes: 57 additions & 27 deletions llvm/test/Transforms/ConstraintElimination/sext.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,7 @@ define i1 @cmp_sext(i32 %a, i32 %b){
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
; CHECK-NEXT: ret i1 [[CMP2]]
; CHECK-NEXT: ret i1 true
; CHECK: else:
; CHECK-NEXT: ret i1 false
;
Expand All @@ -31,64 +30,66 @@ else:
ret i1 false
}

define i1 @cmp_sext_positive_increment(i32 %a, i32 %b, i64 %c){
; CHECK-LABEL: define i1 @cmp_sext_positive_increment(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) {
define i1 @cmp_sext_add(i32 %a, i32 %b){
; CHECK-LABEL: define i1 @cmp_sext_add(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[POS:%.*]] = icmp sgt i64 [[C]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[POS]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
; CHECK: then:
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], [[C]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
; CHECK-NEXT: ret i1 [[CMP2]]
; CHECK-NEXT: [[A1:%.*]] = add nsw i32 [[A]], 1
; CHECK-NEXT: [[B1:%.*]] = add nsw i32 [[B]], 1
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A1]] to i64
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B1]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: ret i1 true
; CHECK: else:
; CHECK-NEXT: ret i1 false
;
entry:
%pos = icmp sgt i64 %c, 0
call void @llvm.assume(i1 %pos)
%cmp = icmp slt i32 %a, %b
br i1 %cmp, label %then, label %else

then:
%sa = sext i32 %a to i64
%sb = sext i32 %b to i64
%add = add nsw i64 %sa, %c
%a1 = add nsw i32 %a, 1
%b1 = add nsw i32 %b, 1
%sa = sext i32 %a1 to i64
%sb = sext i32 %b1 to i64
%add = add nsw i64 %sa, 1
%cmp2 = icmp sge i64 %sb, %add
ret i1 %cmp2

else:
ret i1 false
}

define i1 @cmp_sext_sgt(i32 %a, i32 %b){
; CHECK-LABEL: define i1 @cmp_sext_sgt(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
define i1 @cmp_sext_dynamic_increment(i32 %a, i32 %b, i64 %c){
; CHECK-LABEL: define i1 @cmp_sext_dynamic_increment(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[POS:%.*]] = icmp slt i64 [[C]], 2
; CHECK-NEXT: call void @llvm.assume(i1 [[POS]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
; CHECK: then:
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[SB]], [[ADD]]
; CHECK-NEXT: ret i1 [[CMP2]]
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], [[C]]
; CHECK-NEXT: ret i1 true
; CHECK: else:
; CHECK-NEXT: ret i1 false
;
entry:
%pos = icmp slt i64 %c, 2
call void @llvm.assume(i1 %pos)
%cmp = icmp slt i32 %a, %b
br i1 %cmp, label %then, label %else

then:
%sa = sext i32 %a to i64
%sb = sext i32 %b to i64
%add = add nsw i64 %sa, 1
%cmp2 = icmp sgt i64 %sb, %add
%add = add nsw i64 %sa, %c
%cmp2 = icmp sge i64 %sb, %add
ret i1 %cmp2

else:
Expand All @@ -105,8 +106,7 @@ define i1 @cmp_zext_nneg(i32 %a, i32 %b){
; CHECK-NEXT: [[SA:%.*]] = zext nneg i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
; CHECK-NEXT: ret i1 [[CMP2]]
; CHECK-NEXT: ret i1 true
; CHECK: else:
; CHECK-NEXT: ret i1 false
;
Expand Down Expand Up @@ -216,3 +216,33 @@ then:
else:
ret i1 false
}

define i1 @cmp_sext_sgt(i32 %a, i32 %b){
; CHECK-LABEL: define i1 @cmp_sext_sgt(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
; CHECK: then:
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[SB]], [[ADD]]
; CHECK-NEXT: ret i1 [[CMP2]]
; CHECK: else:
; CHECK-NEXT: ret i1 false
;
entry:
%cmp = icmp slt i32 %a, %b
br i1 %cmp, label %then, label %else

then:
%sa = sext i32 %a to i64
%sb = sext i32 %b to i64
%add = add nsw i64 %sa, 1
%cmp2 = icmp sgt i64 %sb, %add
ret i1 %cmp2

else:
ret i1 false
}