Revert "[GISEL] Add IRTranslation for shufflevector on scalable vector types" #84330
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…r types …" This reverts commit 2b8aaef.
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@llvm/pr-subscribers-llvm-support @llvm/pr-subscribers-backend-aarch64 Author: Michael Maitland (michaelmaitland) ChangesReverts llvm/llvm-project#80378 causing Buildbot failures that did not show up with check-llvm or CI. Patch is 111.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/84330.diff 15 Files Affected:
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index dda367607d04326..33b0152bd7b49c6 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -639,11 +639,6 @@ Concatenate two vectors and shuffle the elements according to the mask operand.
The mask operand should be an IR Constant which exactly matches the
corresponding mask for the IR shufflevector instruction.
-G_SPLAT_VECTOR
-^^^^^^^^^^^^^^^^
-
-Create a vector where all elements are the scalar from the source operand.
-
Vector Reduction Operations
---------------------------
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 6762b1b360d5e81..1387a0a37561c4b 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1063,7 +1063,8 @@ class MachineIRBuilder {
/// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
/// the number of elements
- MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src);
+ MachineInstrBuilder buildSplatVector(const DstOp &Res,
+ const SrcOp &Src);
/// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
///
@@ -1098,15 +1099,6 @@ class MachineIRBuilder {
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
const SrcOp &Src2, ArrayRef<int> Mask);
- /// Build and insert \p Res = G_SPLAT_VECTOR \p Val
- ///
- /// \pre setBasicBlock or setMI must have been called.
- /// \pre \p Res must be a generic virtual register with vector type.
- /// \pre \p Val must be a generic virtual register with scalar type.
- ///
- /// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val);
-
/// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
///
/// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 94fba491148b2ea..6aded2ceebe13a0 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -736,9 +736,6 @@ HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
/// Generic shufflevector.
HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
-/// Generic splatvector.
-HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR)
-
/// Generic count trailing zeroes.
HANDLE_TARGET_OPCODE(G_CTTZ)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index d967885aa2d7587..d2036e478d18f2d 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1450,13 +1450,6 @@ def G_SHUFFLE_VECTOR: GenericInstruction {
let hasSideEffects = false;
}
-// Generic splatvector.
-def G_SPLAT_VECTOR: GenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type1:$val);
- let hasSideEffects = false;
-}
-
//------------------------------------------------------------------------------
// Vector reductions
//------------------------------------------------------------------------------
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
index 1869e0d41a51f63..64e2d517e3b9c48 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -309,7 +309,7 @@ MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res,
// For vectors, CSE the element only for now.
LLT Ty = Res.getLLTTy(*getMRI());
if (Ty.isVector())
- return buildSplatBuildVector(Res, buildConstant(Ty.getElementType(), Val));
+ return buildSplatVector(Res, buildConstant(Ty.getElementType(), Val));
FoldingSetNodeID ID;
GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
@@ -336,7 +336,7 @@ MachineInstrBuilder CSEMIRBuilder::buildFConstant(const DstOp &Res,
// For vectors, CSE the element only for now.
LLT Ty = Res.getLLTTy(*getMRI());
if (Ty.isVector())
- return buildSplatBuildVector(Res, buildFConstant(Ty.getElementType(), Val));
+ return buildSplatVector(Res, buildFConstant(Ty.getElementType(), Val));
FoldingSetNodeID ID;
GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 365870f540daeb8..7c986dbbc2c7c88 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1598,10 +1598,10 @@ bool IRTranslator::translateGetElementPtr(const User &U,
// We might need to splat the base pointer into a vector if the offsets
// are vectors.
if (WantSplatVector && !PtrTy.isVector()) {
- BaseReg = MIRBuilder
- .buildSplatBuildVector(LLT::fixed_vector(VectorWidth, PtrTy),
- BaseReg)
- .getReg(0);
+ BaseReg =
+ MIRBuilder
+ .buildSplatVector(LLT::fixed_vector(VectorWidth, PtrTy), BaseReg)
+ .getReg(0);
PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
PtrTy = getLLTForType(*PtrIRTy, *DL);
OffsetIRTy = DL->getIndexType(PtrIRTy);
@@ -1639,10 +1639,8 @@ bool IRTranslator::translateGetElementPtr(const User &U,
LLT IdxTy = MRI->getType(IdxReg);
if (IdxTy != OffsetTy) {
if (!IdxTy.isVector() && WantSplatVector) {
- IdxReg = MIRBuilder
- .buildSplatBuildVector(OffsetTy.changeElementType(IdxTy),
- IdxReg)
- .getReg(0);
+ IdxReg = MIRBuilder.buildSplatVector(
+ OffsetTy.changeElementType(IdxTy), IdxReg).getReg(0);
}
IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
@@ -2999,19 +2997,6 @@ bool IRTranslator::translateExtractElement(const User &U,
bool IRTranslator::translateShuffleVector(const User &U,
MachineIRBuilder &MIRBuilder) {
- // A ShuffleVector that has operates on scalable vectors is a splat vector
- // where the value of the splat vector is the 0th element of the first
- // operand, since the index mask operand is the zeroinitializer (undef and
- // poison are treated as zeroinitializer here).
- if (U.getOperand(0)->getType()->isScalableTy()) {
- Value *Op0 = U.getOperand(0);
- auto SplatVal = MIRBuilder.buildExtractVectorElementConstant(
- LLT::scalar(Op0->getType()->getScalarSizeInBits()),
- getOrCreateVReg(*Op0), 0);
- MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal);
- return true;
- }
-
ArrayRef<int> Mask;
if (auto *SVI = dyn_cast<ShuffleVectorInst>(&U))
Mask = SVI->getShuffleMask();
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 2ec47f72aca39a2..1d016e684c48f60 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -8391,7 +8391,7 @@ static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
// For vector types create a G_BUILD_VECTOR.
if (Ty.isVector())
- Val = MIB.buildSplatBuildVector(Ty, Val).getReg(0);
+ Val = MIB.buildSplatVector(Ty, Val).getReg(0);
return Val;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index a5a136e2effc602..cdd605a5221ad80 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -326,7 +326,7 @@ MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
auto Const = buildInstr(TargetOpcode::G_CONSTANT)
.addDef(getMRI()->createGenericVirtualRegister(EltTy))
.addCImm(&Val);
- return buildSplatBuildVector(Res, Const);
+ return buildSplatVector(Res, Const);
}
auto Const = buildInstr(TargetOpcode::G_CONSTANT);
@@ -363,7 +363,7 @@ MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
.addDef(getMRI()->createGenericVirtualRegister(EltTy))
.addFPImm(&Val);
- return buildSplatBuildVector(Res, Const);
+ return buildSplatVector(Res, Const);
}
auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
@@ -711,8 +711,8 @@ MachineIRBuilder::buildBuildVectorConstant(const DstOp &Res,
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
}
-MachineInstrBuilder MachineIRBuilder::buildSplatBuildVector(const DstOp &Res,
- const SrcOp &Src) {
+MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
+ const SrcOp &Src) {
SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
}
@@ -742,14 +742,6 @@ MachineInstrBuilder MachineIRBuilder::buildShuffleSplat(const DstOp &Res,
return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
}
-MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
- const SrcOp &Src) {
- LLT DstTy = Res.getLLTTy(*getMRI());
- assert(Src.getLLTTy(*getMRI()) == DstTy.getElementType() &&
- "Expected Src to match Dst elt ty");
- return buildInstr(TargetOpcode::G_SPLAT_VECTOR, Res, Src);
-}
-
MachineInstrBuilder MachineIRBuilder::buildShuffleVector(const DstOp &Res,
const SrcOp &Src1,
const SrcOp &Src2,
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index ecb3bd33bdfd492..1d0757c5d7f5f59 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1640,24 +1640,6 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
break;
}
-
- case TargetOpcode::G_SPLAT_VECTOR: {
- LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
- LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
-
- if (!DstTy.isScalableVector())
- report("Destination type must be a scalable vector", MI);
-
- if (!SrcTy.isScalar())
- report("Source type must be a scalar", MI);
-
- if (DstTy.getScalarType() != SrcTy)
- report("Element type of the destination must be the same type as the "
- "source type",
- MI);
-
- break;
- }
case TargetOpcode::G_DYN_STACKALLOC: {
const MachineOperand &DstOp = MI->getOperand(0);
const MachineOperand &AllocOp = MI->getOperand(1);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4713bd605c243b6..750d70c03eabd79 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20920,8 +20920,7 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
unsigned Op = Inst.getOpcode();
if (Op == Instruction::Add || Op == Instruction::Sub ||
Op == Instruction::And || Op == Instruction::Or ||
- Op == Instruction::Xor || Op == Instruction::InsertElement ||
- Op == Instruction::Xor || Op == Instruction::ShuffleVector)
+ Op == Instruction::Xor || Op == Instruction::InsertElement)
return false;
if (Inst.getType()->isScalableTy())
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 7774158e15ec581..d87704cf45d5d5c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -625,9 +625,6 @@
# DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_SPLAT_VECTOR (opcode 217): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
deleted file mode 100644
index df7778899b0d094..000000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
+++ /dev/null
@@ -1,1774 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
-; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
-; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
-
-define <vscale x 1 x i1> @shufflevector_nxv1i1_0() {
- ; RV32-LABEL: name: shufflevector_nxv1i1_0
- ; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s64)
- ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
- ; RV32-NEXT: PseudoRET implicit $v0
- ;
- ; RV64-LABEL: name: shufflevector_nxv1i1_0
- ; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s64)
- ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
- ; RV64-NEXT: PseudoRET implicit $v0
- %a = shufflevector <vscale x 1 x i1> poison, <vscale x 1 x i1> poison, <vscale x 1 x i32> poison
- ret <vscale x 1 x i1> %a
-}
-
-define <vscale x 1 x i1> @shufflevector_nxv1i1_1() {
- ; RV32-LABEL: name: shufflevector_nxv1i1_1
- ; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s64)
- ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
- ; RV32-NEXT: PseudoRET implicit $v0
- ;
- ; RV64-LABEL: name: shufflevector_nxv1i1_1
- ; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s64)
- ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
- ; RV64-NEXT: PseudoRET implicit $v0
- %a = shufflevector <vscale x 1 x i1> undef, <vscale x 1 x i1> undef, <vscale x 1 x i32> undef
- ret <vscale x 1 x i1> %a
-}
-
-define <vscale x 1 x i1> @shufflevector_nxv1i1_2(<vscale x 1 x i1> %a) {
- ; RV32-LABEL: name: shufflevector_nxv1i1_2
- ; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: liveins: $v0
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s1>), [[C]](s64)
- ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
- ; RV32-NEXT: PseudoRET implicit $v0
- ;
- ; RV64-LABEL: name: shufflevector_nxv1i1_2
- ; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: liveins: $v0
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s1>), [[C]](s64)
- ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
- ; RV64-NEXT: PseudoRET implicit $v0
- %b = shufflevector <vscale x 1 x i1> %a , <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
- ret <vscale x 1 x i1> %b
-}
-
-define <vscale x 2 x i1> @shufflevector_nxv2i1_0() {
- ; RV32-LABEL: name: shufflevector_nxv2i1_0
- ; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s64)
- ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)
- ; RV32-NEXT: PseudoRET implicit $v0
- ;
- ; RV64-LABEL: name: shufflevector_nxv2i1_0
- ; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s64)
- ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)
- ; RV64-NEXT: PseudoRET implicit $v0
- %a = shufflevector <vscale x 2 x i1> poison, <vscale x 2 x i1> poison, <vscale x 2 x i32> poison
- ret <vscale x 2 x i1> %a
-}
-
-define <vscale x 2 x i1> @shufflevector_nxv2i1_1() {
- ; RV32-LABEL: name: shufflevector_nxv2i1_1
- ; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s64)
- ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)
- ; RV32-NEXT: PseudoRET implicit $v0
- ;
- ; RV64-LABEL: name: shufflevector_nxv2i1_1
- ; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s64)
- ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)
- ; RV64-NEXT: PseudoRET implicit $v0
- %a = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> undef
- ret <vscale x 2 x i1> %a
-}
-
-define <vscale x 2 x i1> @shufflevector_nxv2i1_2(<vscale x 2 x i1> %a) {
- ; RV32-LABEL: name: shufflevector_nxv2i1_2
- ; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: liveins: $v0
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s1>), [[C]](s64)
- ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
- ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)
- ; RV32-NEXT: PseudoRET implicit $v0
- ;
- ; RV64-LABEL: name: shufflevector_nxv2i1_2
- ; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: liveins: $v0
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COP...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff 9e0f5909d0af3911b19bb1f97fb400c3ce431f63 4a1435f3b2d2f80d09f8747fed771811ccb65eb4 -- llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp llvm/lib/CodeGen/MachineVerifier.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cppView the diff from clang-format here.diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 1387a0a375..3ef0157abe 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1063,8 +1063,7 @@ public:
/// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
/// the number of elements
- MachineInstrBuilder buildSplatVector(const DstOp &Res,
- const SrcOp &Src);
+ MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src);
/// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
///
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 7c986dbbc2..e70f70c61b 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1639,8 +1639,10 @@ bool IRTranslator::translateGetElementPtr(const User &U,
LLT IdxTy = MRI->getType(IdxReg);
if (IdxTy != OffsetTy) {
if (!IdxTy.isVector() && WantSplatVector) {
- IdxReg = MIRBuilder.buildSplatVector(
- OffsetTy.changeElementType(IdxTy), IdxReg).getReg(0);
+ IdxReg =
+ MIRBuilder
+ .buildSplatVector(OffsetTy.changeElementType(IdxTy), IdxReg)
+ .getReg(0);
}
IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
|
michaelmaitland
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Mar 7, 2024
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Per: https://llvm.org/docs/CodeReview.html#code-review-workflow if you're just creating PRs for precommit checking/revert convenience, please apply the |
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Reverts #80378
causing Buildbot failures that did not show up with check-llvm or CI.