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[AArch64] Replace AND with LSL#2 for LDR target (#34101) #89531

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Merged
merged 2 commits into from
Aug 24, 2024
Merged

[AArch64] Replace AND with LSL#2 for LDR target (#34101) #89531

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33d7398
[AArch64] Add tests for prevent (shl (srl x, c1), c2) -> (and (shift …
ParkHanbum May 31, 2024
c956250
[AArch64] prevent (shl (srl x, c1), c2) -> (and (shift x, c3)) when load
ParkHanbum Apr 22, 2024
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17 changes: 17 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18012,6 +18012,23 @@ bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
return (!C1 || !C2 || C1->getZExtValue() >= C2->getZExtValue());
}

// We do not need to fold when this shifting used in specific load case:
// (ldr x, (add x, (shl (srl x, c1) 2)))
if (N->getOpcode() == ISD::SHL && N->hasOneUse()) {
if (auto C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
unsigned ShlAmt = C2->getZExtValue();
if (auto ShouldADD = *N->use_begin();
ShouldADD->getOpcode() == ISD::ADD && ShouldADD->hasOneUse()) {
if (auto ShouldLOAD = dyn_cast<LoadSDNode>(*ShouldADD->use_begin())) {
unsigned ByteVT = ShouldLOAD->getMemoryVT().getSizeInBits() / 8;
if ((1ULL << ShlAmt) == ByteVT &&
isIndexedLoadLegal(ISD::PRE_INC, ShouldLOAD->getMemoryVT()))
return false;
}
}
}
}

return true;
}

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138 changes: 138 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-fold-lshr.ll
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@@ -0,0 +1,138 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
;

define i16 @load16_shr63(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load16_shr63:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #63
; CHECK-NEXT: ldrh w0, [x2, x8, lsl #1]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 63
%arrayidx = getelementptr inbounds i16, ptr %table, i64 %shr
%0 = load i16, ptr %arrayidx, align 2
ret i16 %0
}

define i16 @load16_shr2(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load16_shr2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #2
; CHECK-NEXT: ldrh w0, [x2, x8, lsl #1]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 2
%arrayidx = getelementptr inbounds i16, ptr %table, i64 %shr
%0 = load i16, ptr %arrayidx, align 2
ret i16 %0
}

define i16 @load16_shr1(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load16_shr1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #1
; CHECK-NEXT: ldrh w0, [x2, x8, lsl #1]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 1
%arrayidx = getelementptr inbounds i16, ptr %table, i64 %shr
%0 = load i16, ptr %arrayidx, align 2
ret i16 %0
}

define i32 @load32_shr63(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load32_shr63:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #63
; CHECK-NEXT: ldr w0, [x2, x8, lsl #2]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 63
%arrayidx = getelementptr inbounds i32, ptr %table, i64 %shr
%0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}

define i32 @load32_shr2(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load32_shr2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #2
; CHECK-NEXT: ldr w0, [x2, x8, lsl #2]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 2
%arrayidx = getelementptr inbounds i32, ptr %table, i64 %shr
%0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}

define i32 @load32_shr1(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load32_shr1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #1
; CHECK-NEXT: ldr w0, [x2, x8, lsl #2]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 1
%arrayidx = getelementptr inbounds i32, ptr %table, i64 %shr
%0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}

define i64 @load64_shr63(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load64_shr63:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #63
; CHECK-NEXT: ldr x0, [x2, x8, lsl #3]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 63
%arrayidx = getelementptr inbounds i64, ptr %table, i64 %shr
%0 = load i64, ptr %arrayidx, align 8
ret i64 %0
}

define i64 @load64_shr2(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load64_shr2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #2
; CHECK-NEXT: ldr x0, [x2, x8, lsl #3]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 2
%arrayidx = getelementptr inbounds i64, ptr %table, i64 %shr
%0 = load i64, ptr %arrayidx, align 8
ret i64 %0
}

define i64 @load64_shr1(i64 %a, i64 %b, ptr %table) {
; CHECK-LABEL: load64_shr1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mul x8, x1, x0
; CHECK-NEXT: lsr x8, x8, #1
; CHECK-NEXT: ldr x0, [x2, x8, lsl #3]
; CHECK-NEXT: ret
entry:
%mul = mul i64 %b, %a
%shr = lshr i64 %mul, 1
%arrayidx = getelementptr inbounds i64, ptr %table, i64 %shr
%0 = load i64, ptr %arrayidx, align 8
ret i64 %0
}
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