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May 3, 2024
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[M68k] Correctly emit non-pic relocations #89863

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4 changes: 2 additions & 2 deletions llvm/lib/Target/M68k/M68kSubtarget.cpp
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Expand Up @@ -251,6 +251,6 @@ M68kSubtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
return M68kII::MO_GOTPCREL;
}

// otherwise linker will figure this out
return M68kII::MO_PLT;
// Ensure that we don't emit PLT relocations when in non-pic modes.
return isPositionIndependent() ? M68kII::MO_PLT : M68kII::MO_ABSOLUTE_ADDRESS;
}
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
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Expand Up @@ -77,7 +77,7 @@ define i32 @test5(i32 %A) nounwind {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: move.l #1577682821, (4,%sp)
; CHECK-NEXT: move.l (16,%sp), (%sp)
; CHECK-NEXT: jsr __udivsi3@PLT
; CHECK-NEXT: jsr __udivsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
Expand Down Expand Up @@ -114,7 +114,7 @@ define i32 @test7(i32 %x) nounwind {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: move.l #28, (4,%sp)
; CHECK-NEXT: move.l (16,%sp), (%sp)
; CHECK-NEXT: jsr __udivsi3@PLT
; CHECK-NEXT: jsr __udivsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
%div = udiv i32 %x, 28
Expand Down Expand Up @@ -178,7 +178,7 @@ define i32 @testsize2(i32 %x) minsize nounwind {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: move.l #33, (4,%sp)
; CHECK-NEXT: move.l (16,%sp), (%sp)
; CHECK-NEXT: jsr __divsi3@PLT
; CHECK-NEXT: jsr __divsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
Expand All @@ -203,7 +203,7 @@ define i32 @testsize4(i32 %x) minsize nounwind {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: move.l #33, (4,%sp)
; CHECK-NEXT: move.l (16,%sp), (%sp)
; CHECK-NEXT: jsr __udivsi3@PLT
; CHECK-NEXT: jsr __udivsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/M68k/Arith/imul.ll
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Expand Up @@ -116,7 +116,7 @@ define i32 @mul_32(i32 %a, i32 %b) {
; CHECK-NEXT: .cfi_def_cfa_offset -16
; CHECK-NEXT: move.l (20,%sp), (4,%sp)
; CHECK-NEXT: move.l (16,%sp), (%sp)
; CHECK-NEXT: jsr __mulsi3@PLT
; CHECK-NEXT: jsr __mulsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
%mul = mul i32 %a, %b
Expand Down Expand Up @@ -162,7 +162,7 @@ define i64 @mul_64(i64 %a, i64 %b) {
; CHECK-NEXT: move.l (32,%sp), (8,%sp)
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
; CHECK-NEXT: move.l (24,%sp), (%sp)
; CHECK-NEXT: jsr __muldi3@PLT
; CHECK-NEXT: jsr __muldi3
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
%mul = mul i64 %a, %b
Expand All @@ -179,7 +179,7 @@ define i64 @mul3_64(i64 %A) {
; CHECK-NEXT: move.l #0, (8,%sp)
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
; CHECK-NEXT: move.l (24,%sp), (%sp)
; CHECK-NEXT: jsr __muldi3@PLT
; CHECK-NEXT: jsr __muldi3
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
%mul = mul i64 %A, 3
Expand All @@ -196,7 +196,7 @@ define i64 @mul40_64(i64 %A) {
; CHECK-NEXT: move.l #0, (8,%sp)
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
; CHECK-NEXT: move.l (24,%sp), (%sp)
; CHECK-NEXT: jsr __muldi3@PLT
; CHECK-NEXT: jsr __muldi3
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
%mul = mul i64 %A, 40
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/M68k/Arith/mul64.ll
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Expand Up @@ -11,7 +11,7 @@ define i64 @foo(i64 %t, i64 %u) nounwind {
; CHECK-NEXT: move.l (32,%sp), (8,%sp)
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
; CHECK-NEXT: move.l (24,%sp), (%sp)
; CHECK-NEXT: jsr __muldi3@PLT
; CHECK-NEXT: jsr __muldi3
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
%k = mul i64 %t, %u
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll
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Expand Up @@ -9,7 +9,7 @@ define i32 @test1(i32 %x) {
; CHECK-NEXT: .cfi_def_cfa_offset -16
; CHECK-NEXT: move.l #-1030792151, (4,%sp)
; CHECK-NEXT: move.l (16,%sp), (%sp)
; CHECK-NEXT: jsr __mulsi3@PLT
; CHECK-NEXT: jsr __mulsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
%div = sdiv exact i32 %x, 25
Expand All @@ -26,7 +26,7 @@ define i32 @test2(i32 %x) {
; CHECK-NEXT: asr.l #3, %d0
; CHECK-NEXT: move.l %d0, (%sp)
; CHECK-NEXT: move.l #-1431655765, (4,%sp)
; CHECK-NEXT: jsr __mulsi3@PLT
; CHECK-NEXT: jsr __mulsi3
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
%div = sdiv exact i32 %x, 24
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
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Expand Up @@ -69,15 +69,15 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: ; %bb.2: ; %overflow
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB3_1: ; %normal
; CHECK-NEXT: move.l %d0, (4,%sp)
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
Expand Down Expand Up @@ -107,15 +107,15 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: ; %bb.1: ; %overflow
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB4_2: ; %normal
; CHECK-NEXT: move.l %d0, (4,%sp)
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
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Expand Up @@ -18,15 +18,15 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: ; %bb.2: ; %overflow
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB0_1: ; %normal
; CHECK-NEXT: move.l %d0, (4,%sp)
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
Expand Down Expand Up @@ -55,15 +55,15 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: ; %bb.2: ; %carry
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB1_1: ; %normal
; CHECK-NEXT: move.l %d0, (4,%sp)
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf@PLT
; CHECK-NEXT: jsr printf
; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/M68k/Atomics/cmpxchg.ll
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Expand Up @@ -18,7 +18,7 @@ define i1 @cmpxchg_i8_monotonic_monotonic(i8 %cmp, i8 %new, ptr %mem) nounwind {
; NO-ATOMIC-NEXT: and.l #255, %d0
; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
; NO-ATOMIC-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_1@PLT
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_1
; NO-ATOMIC-NEXT: sub.b %d2, %d0
; NO-ATOMIC-NEXT: seq %d0
; NO-ATOMIC-NEXT: movem.l (16,%sp), %d2 ; 8-byte Folded Reload
Expand Down Expand Up @@ -55,7 +55,7 @@ define i16 @cmpxchg_i16_release_monotonic(i16 %cmp, i16 %new, ptr %mem) nounwind
; NO-ATOMIC-NEXT: and.l #65535, %d0
; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_2@PLT
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_2
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -78,7 +78,7 @@ define i32 @cmpxchg_i32_release_acquire(i32 %cmp, i32 %new, ptr %mem) nounwind {
; NO-ATOMIC-NEXT: move.l (20,%sp), (8,%sp)
; NO-ATOMIC-NEXT: move.l (16,%sp), (4,%sp)
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_4@PLT
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_4
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
Expand Down Expand Up @@ -107,7 +107,7 @@ define i64 @cmpxchg_i64_seqcst_seqcst(i64 %cmp, i64 %new, ptr %mem) nounwind {
; NO-ATOMIC-NEXT: move.l (52,%sp), (12,%sp)
; NO-ATOMIC-NEXT: move.l (48,%sp), (8,%sp)
; NO-ATOMIC-NEXT: move.l (56,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8
; NO-ATOMIC-NEXT: move.l (28,%sp), %d1
; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
; NO-ATOMIC-NEXT: adda.l #36, %sp
Expand All @@ -125,7 +125,7 @@ define i64 @cmpxchg_i64_seqcst_seqcst(i64 %cmp, i64 %new, ptr %mem) nounwind {
; ATOMIC-NEXT: move.l (52,%sp), (12,%sp)
; ATOMIC-NEXT: move.l (48,%sp), (8,%sp)
; ATOMIC-NEXT: move.l (56,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_compare_exchange_8@PLT
; ATOMIC-NEXT: jsr __atomic_compare_exchange_8
; ATOMIC-NEXT: move.l (28,%sp), %d1
; ATOMIC-NEXT: move.l (24,%sp), %d0
; ATOMIC-NEXT: adda.l #36, %sp
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/M68k/Atomics/load-store.ll
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Expand Up @@ -203,7 +203,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_load_8
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -212,7 +212,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
; ATOMIC-NEXT: suba.l #12, %sp
; ATOMIC-NEXT: move.l #0, (4,%sp)
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
; ATOMIC-NEXT: jsr __atomic_load_8
; ATOMIC-NEXT: adda.l #12, %sp
; ATOMIC-NEXT: rts
%1 = load atomic i64, ptr %a unordered, align 8
Expand All @@ -225,7 +225,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_load_8
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -234,7 +234,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
; ATOMIC-NEXT: suba.l #12, %sp
; ATOMIC-NEXT: move.l #0, (4,%sp)
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
; ATOMIC-NEXT: jsr __atomic_load_8
; ATOMIC-NEXT: adda.l #12, %sp
; ATOMIC-NEXT: rts
%1 = load atomic i64, ptr %a monotonic, align 8
Expand All @@ -247,7 +247,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: move.l #2, (4,%sp)
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_load_8
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -256,7 +256,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
; ATOMIC-NEXT: suba.l #12, %sp
; ATOMIC-NEXT: move.l #2, (4,%sp)
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
; ATOMIC-NEXT: jsr __atomic_load_8
; ATOMIC-NEXT: adda.l #12, %sp
; ATOMIC-NEXT: rts
%1 = load atomic i64, ptr %a acquire, align 8
Expand All @@ -269,7 +269,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: move.l #5, (4,%sp)
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_load_8
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -278,7 +278,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
; ATOMIC-NEXT: suba.l #12, %sp
; ATOMIC-NEXT: move.l #5, (4,%sp)
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
; ATOMIC-NEXT: jsr __atomic_load_8
; ATOMIC-NEXT: adda.l #12, %sp
; ATOMIC-NEXT: rts
%1 = load atomic i64, ptr %a seq_cst, align 8
Expand Down Expand Up @@ -509,7 +509,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %val) nounwind {
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_store_8
; NO-ATOMIC-NEXT: adda.l #20, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -520,7 +520,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %val) nounwind {
; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; ATOMIC-NEXT: move.l (24,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
; ATOMIC-NEXT: jsr __atomic_store_8
; ATOMIC-NEXT: adda.l #20, %sp
; ATOMIC-NEXT: rts
store atomic i64 %val, ptr %a unordered, align 8
Expand All @@ -535,7 +535,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %val) nounwind {
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_store_8
; NO-ATOMIC-NEXT: adda.l #20, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -546,7 +546,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %val) nounwind {
; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; ATOMIC-NEXT: move.l (24,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
; ATOMIC-NEXT: jsr __atomic_store_8
; ATOMIC-NEXT: adda.l #20, %sp
; ATOMIC-NEXT: rts
store atomic i64 %val, ptr %a monotonic, align 8
Expand All @@ -561,7 +561,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %val) nounwind {
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_store_8
; NO-ATOMIC-NEXT: adda.l #20, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -572,7 +572,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %val) nounwind {
; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; ATOMIC-NEXT: move.l (24,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
; ATOMIC-NEXT: jsr __atomic_store_8
; ATOMIC-NEXT: adda.l #20, %sp
; ATOMIC-NEXT: rts
store atomic i64 %val, ptr %a release, align 8
Expand All @@ -587,7 +587,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind {
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
; NO-ATOMIC-NEXT: jsr __atomic_store_8
; NO-ATOMIC-NEXT: adda.l #20, %sp
; NO-ATOMIC-NEXT: rts
;
Expand All @@ -598,7 +598,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind {
; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
; ATOMIC-NEXT: move.l (24,%sp), (%sp)
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
; ATOMIC-NEXT: jsr __atomic_store_8
; ATOMIC-NEXT: adda.l #20, %sp
; ATOMIC-NEXT: rts
store atomic i64 %val, ptr %a seq_cst, align 8
Expand Down
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