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[AMDGPU][AsmParser][NFC] Generate NamedIntOperand predicates automatically. #90576

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Merged
merged 1 commit into from
May 1, 2024
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[AMDGPU][AsmParser][NFC] Generate NamedIntOperand predicates automatically. #90576

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38 changes: 0 additions & 38 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -376,17 +376,13 @@ class AMDGPUOperand : public MCParsedAsmOperand {
}

bool isOModSI() const { return isImmTy(ImmTyOModSI); }
bool isDMask() const { return isImmTy(ImmTyDMask); }
bool isDim() const { return isImmTy(ImmTyDim); }
bool isR128A16() const { return isImmTy(ImmTyR128A16); }
bool isOff() const { return isImmTy(ImmTyOff); }
bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
bool isOffen() const { return isImmTy(ImmTyOffen); }
bool isIdxen() const { return isImmTy(ImmTyIdxen); }
bool isAddr64() const { return isImmTy(ImmTyAddr64); }
bool isOffset() const { return isImmTy(ImmTyOffset); }
bool isOffset0() const { return isImmTy(ImmTyOffset0); }
bool isOffset1() const { return isImmTy(ImmTyOffset1); }
bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }
bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); }
bool isGDS() const { return isImmTy(ImmTyGDS); }
Expand All @@ -396,9 +392,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isIndexKey16bit() const { return isImmTy(ImmTyIndexKey16bit); }
bool isTFE() const { return isImmTy(ImmTyTFE); }
bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }
bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }
bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }
bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
bool isDppFI() const { return isImmTy(ImmTyDppFI); }
bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }
bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }
Expand All @@ -411,7 +404,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
bool isNegHi() const { return isImmTy(ImmTyNegHi); }
bool isByteSel() const { return isImmTy(ImmTyByteSel); }

bool isRegOrImm() const {
return isReg() || isImm();
Expand Down Expand Up @@ -949,16 +941,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isDPP8() const;
bool isDPPCtrl() const;
bool isBLGP() const;
bool isCBSZ() const;
bool isABID() const;
bool isGPRIdxMode() const;
bool isS16Imm() const;
bool isU16Imm() const;
bool isEndpgm() const;
bool isWaitVDST() const;
bool isWaitEXP() const;
bool isWaitVAVDst() const;
bool isWaitVMVSrc() const;

auto getPredicate(std::function<bool(const AMDGPUOperand &Op)> P) const {
return std::bind(P, *this);
Expand Down Expand Up @@ -8936,14 +8922,6 @@ bool AMDGPUOperand::isBLGP() const {
return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());
}

bool AMDGPUOperand::isCBSZ() const {
return isImm() && getImmTy() == ImmTyCBSZ;
}

bool AMDGPUOperand::isABID() const {
return isImm() && getImmTy() == ImmTyABID;
}

bool AMDGPUOperand::isS16Imm() const {
return isImmLiteral() && (isInt<16>(getImm()) || isUInt<16>(getImm()));
}
Expand Down Expand Up @@ -9664,22 +9642,6 @@ ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {

bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }

//===----------------------------------------------------------------------===//
// LDSDIR
//===----------------------------------------------------------------------===//

bool AMDGPUOperand::isWaitVDST() const { return isImmTy(ImmTyWaitVDST); }

bool AMDGPUOperand::isWaitVAVDst() const { return isImmTy(ImmTyWaitVAVDst); }

bool AMDGPUOperand::isWaitVMVSrc() const { return isImmTy(ImmTyWaitVMVSrc); }

//===----------------------------------------------------------------------===//
// VINTERP
//===----------------------------------------------------------------------===//

bool AMDGPUOperand::isWaitEXP() const { return isImmTy(ImmTyWaitEXP); }

//===----------------------------------------------------------------------===//
// Split Barrier
//===----------------------------------------------------------------------===//
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1002,6 +1002,9 @@ def SDWAVopcDst : BoolRC {
class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
string name = NAME>
: CustomOperand<Type, Optional, name> {
let PredicateMethod =
"getPredicate([](const AMDGPUOperand &Op) -> bool { "#
"return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })";
string Validator = "[](int64_t V) { return true; }";
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
let ParserMethod =
Expand Down
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