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[InterleavedLoadCombine] Bail out on non-byte-sized vector element type #90705

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Merged
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May 2, 2024
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[InterleavedLoadCombine] Bail out on non-byte-sized vector element type #90705

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3 changes: 3 additions & 0 deletions llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -877,6 +877,9 @@ struct VectorInfo {
if (LI->isAtomic())
return false;

if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType()))
return false;

// Get the base polynomial
computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, DL);

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19 changes: 19 additions & 0 deletions llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
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@@ -0,0 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s

target triple = "aarch64-unknown-windows-gnu"
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never seen this triple before :)

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image

It's one of our CI machines over at the Zig project :-)


; Make sure we don't crash on loads of vectors of non-byte-sized types.
define <4 x i1> @test(ptr %p) {
; CHECK-LABEL: define <4 x i1> @test(
; CHECK-SAME: ptr [[P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: ret <4 x i1> [[SHUF]]
;
entry:
%load = load <2 x i1>, ptr %p, align 1
%shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
ret <4 x i1> %shuf
}
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