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[LoongArch] Optimize codegen for ISD::{ROTL,ROTR} #91174

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Merged
merged 3 commits into from
May 7, 2024
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[LoongArch] Optimize codegen for ISD::{ROTL,ROTR} #91174

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4308d79
[LoongArch] Optimize codegen for ISD::ROTL
heiher May 6, 2024
cf550b1
Address SixWeining's comment
heiher May 7, 2024
d39c546
Address wangleiat's comments
heiher May 7, 2024
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17 changes: 9 additions & 8 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1671,10 +1671,9 @@ static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode) {
return LoongArchISD::SRA_W;
case ISD::SRL:
return LoongArchISD::SRL_W;
case ISD::ROTL:
case ISD::ROTR:
return LoongArchISD::ROTR_W;
case ISD::ROTL:
return LoongArchISD::ROTL_W;
case ISD::CTTZ:
return LoongArchISD::CTZ_W;
case ISD::CTLZ:
Expand Down Expand Up @@ -1704,6 +1703,10 @@ static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp,
case 2: {
NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));
if (N->getOpcode() == ISD::ROTL) {
SDValue TmpOp = DAG.getConstant(32, DL, MVT::i64);
NewOp1 = DAG.getNode(ISD::SUB, DL, MVT::i64, TmpOp, NewOp1);
}
NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
break;
}
Expand Down Expand Up @@ -1841,7 +1844,6 @@ void LoongArchTargetLowering::ReplaceNodeResults(
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
case ISD::ROTR:
assert(VT == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
if (N->getOperand(1).getOpcode() != ISD::Constant) {
Expand All @@ -1850,11 +1852,10 @@ void LoongArchTargetLowering::ReplaceNodeResults(
}
break;
case ISD::ROTL:
ConstantSDNode *CN;
if ((CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))) {
Results.push_back(customLegalizeToWOp(N, DAG, 2));
break;
}
case ISD::ROTR:
assert(VT == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
Results.push_back(customLegalizeToWOp(N, DAG, 2));
break;
case ISD::FP_TO_SINT: {
assert(VT == MVT::i32 && Subtarget.is64Bit() &&
Expand Down
7 changes: 2 additions & 5 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
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Expand Up @@ -85,7 +85,6 @@ def loongarch_sll_w : SDNode<"LoongArchISD::SLL_W", SDT_LoongArchIntBinOpW>;
def loongarch_sra_w : SDNode<"LoongArchISD::SRA_W", SDT_LoongArchIntBinOpW>;
def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
def loongarch_rotl_w : SDNode<"LoongArchISD::ROTL_W", SDT_LoongArchIntBinOpW>;
def loongarch_crc_w_b_w
: SDNode<"LoongArchISD::CRC_W_B_W", SDT_LoongArchIntBinOpW, [SDNPHasChain]>;
def loongarch_crc_w_h_w
Expand Down Expand Up @@ -1116,12 +1115,10 @@ def : PatGprGpr<srem, MOD_D>;
def : PatGprGpr<urem, MOD_DU>;
def : PatGprGpr<rotr, ROTR_D>;
def : PatGprGpr<loongarch_rotr_w, ROTR_W>;
def : PatGprGpr_32<rotr, ROTR_W>;
def : PatGprImm<rotr, ROTRI_D, uimm6>;
def : PatGprImm_32<rotr, ROTRI_W, uimm5>;
def : Pat<(loongarch_rotl_w GPR:$rj, uimm5:$imm),
(ROTRI_W GPR:$rj, (ImmSubFrom32 uimm5:$imm))>;
def : Pat<(sext_inreg (loongarch_rotl_w GPR:$rj, uimm5:$imm), i32),
(ROTRI_W GPR:$rj, (ImmSubFrom32 uimm5:$imm))>;
def : PatGprImm<loongarch_rotr_w, ROTRI_W, uimm5>;
// TODO: Select "_W[U]" instructions for i32xi32 if only lower 32 bits of the
// product are used.
def : PatGprGpr<mul, MUL_D>;
Expand Down
35 changes: 13 additions & 22 deletions llvm/test/CodeGen/LoongArch/rotl-rotr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64

;; TODO: Add optimization to ISD::ROTL

define signext i32 @rotl_32(i32 signext %x, i32 signext %y) nounwind {
; LA32-LABEL: rotl_32:
; LA32: # %bb.0:
Expand All @@ -14,10 +12,9 @@ define signext i32 @rotl_32(i32 signext %x, i32 signext %y) nounwind {
;
; LA64-LABEL: rotl_32:
; LA64: # %bb.0:
; LA64-NEXT: sll.w $a2, $a0, $a1
; LA64-NEXT: sub.d $a1, $zero, $a1
; LA64-NEXT: srl.w $a0, $a0, $a1
; LA64-NEXT: or $a0, $a2, $a0
; LA64-NEXT: ori $a2, $zero, 32
; LA64-NEXT: sub.d $a1, $a2, $a1
; LA64-NEXT: rotr.w $a0, $a0, $a1
; LA64-NEXT: ret
%z = sub i32 32, %y
%b = shl i32 %x, %y
Expand Down Expand Up @@ -152,10 +149,9 @@ define signext i32 @rotl_32_mask(i32 signext %x, i32 signext %y) nounwind {
;
; LA64-LABEL: rotl_32_mask:
; LA64: # %bb.0:
; LA64-NEXT: sll.w $a2, $a0, $a1
; LA64-NEXT: sub.d $a1, $zero, $a1
; LA64-NEXT: srl.w $a0, $a0, $a1
; LA64-NEXT: or $a0, $a2, $a0
; LA64-NEXT: ori $a2, $zero, 32
; LA64-NEXT: sub.d $a1, $a2, $a1
; LA64-NEXT: rotr.w $a0, $a0, $a1
; LA64-NEXT: ret
%z = sub i32 0, %y
%and = and i32 %z, 31
Expand All @@ -174,10 +170,9 @@ define signext i32 @rotl_32_mask_and_63_and_31(i32 signext %x, i32 signext %y) n
;
; LA64-LABEL: rotl_32_mask_and_63_and_31:
; LA64: # %bb.0:
; LA64-NEXT: sll.w $a2, $a0, $a1
; LA64-NEXT: sub.d $a1, $zero, $a1
; LA64-NEXT: srl.w $a0, $a0, $a1
; LA64-NEXT: or $a0, $a2, $a0
; LA64-NEXT: ori $a2, $zero, 32
; LA64-NEXT: sub.d $a1, $a2, $a1
; LA64-NEXT: rotr.w $a0, $a0, $a1
; LA64-NEXT: ret
%a = and i32 %y, 63
%b = shl i32 %x, %a
Expand All @@ -197,10 +192,9 @@ define signext i32 @rotl_32_mask_or_64_or_32(i32 signext %x, i32 signext %y) nou
;
; LA64-LABEL: rotl_32_mask_or_64_or_32:
; LA64: # %bb.0:
; LA64-NEXT: sll.w $a2, $a0, $a1
; LA64-NEXT: sub.d $a1, $zero, $a1
; LA64-NEXT: srl.w $a0, $a0, $a1
; LA64-NEXT: or $a0, $a2, $a0
; LA64-NEXT: ori $a2, $zero, 32
; LA64-NEXT: sub.d $a1, $a2, $a1
; LA64-NEXT: rotr.w $a0, $a0, $a1
; LA64-NEXT: ret
%a = or i32 %y, 64
%b = shl i32 %x, %a
Expand Down Expand Up @@ -591,10 +585,7 @@ define signext i32 @rotr_i32_fshr(i32 signext %a) nounwind {
;
; LA64-LABEL: rotr_i32_fshr:
; LA64: # %bb.0:
; LA64-NEXT: slli.d $a1, $a0, 20
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 12
; LA64-NEXT: or $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: rotri.w $a0, $a0, 12
; LA64-NEXT: ret
%or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 12)
ret i32 %or
Expand Down
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