[VPlan] Add scalar inferencing support for addrspace cast

[PietroGhg]

Fixes #91434

[llvmbot]

@llvm/pr-subscribers-llvm-transforms

Author: None (PietroGhg)

Changes

This PR addresses #91434

---

Full diff: https://github.com/llvm/llvm-project/pull/92107.diff

2 Files Affected:

• (modified) llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp (+1)
• (added) llvm/test/Transforms/LoopVectorize/as_cast.ll (+21)

diff --git a/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp b/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
index 5f93339083f0c..681cb43d44f66 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
@@ -185,6 +185,7 @@ Type *VPTypeAnalysis::inferScalarTypeForRecipe(const VPReplicateRecipe *R) {
   case Instruction::FPToUI:
   case Instruction::PtrToInt:
   case Instruction::IntToPtr:
+  case Instruction::AddrSpaceCast:
     return R->getUnderlyingInstr()->getType();
   case Instruction::Freeze:
   case Instruction::FNeg:
diff --git a/llvm/test/Transforms/LoopVectorize/as_cast.ll b/llvm/test/Transforms/LoopVectorize/as_cast.ll
new file mode 100644
index 0000000000000..ff5f818e95e45
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/as_cast.ll
@@ -0,0 +1,21 @@
+; RUN: opt -passes=loop-vectorize %s
+; ModuleID = '<bc file>'
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @foo(ptr addrspace(1) %in) {
+entry:
+  br label %for.body.i.epil
+
+for.body.i.epil:                                  ; preds = %for.body.i.epil, %entry
+  %epil.iter = phi i64 [ %epil.iter.next, %for.body.i.epil ], [ 0, %entry ]
+  %arrayidx.ascast.i.epil = addrspacecast ptr addrspace(1) %in to ptr
+  %epil.iter.next = add i64 %epil.iter, 1
+  %arrayidx = getelementptr inbounds i64, ptr %arrayidx.ascast.i.epil, i64 %epil.iter.next
+  store i64 %epil.iter.next, ptr %arrayidx, align 4
+  %epil.iter.cmp.not = icmp eq i64 %epil.iter.next, 7
+  br i1 %epil.iter.cmp.not, label %loop.exit, label %for.body.i.epil
+
+loop.exit: ; preds = %for.body.i.epil
+  ret void
+}

[fhahn]

Does this test depend on the X86 backend? Can you remove this and instead use the force-vector-width flag? Also please check the output.

[PietroGhg]

It doesn't depend on the X86 backend, I've set the right flags to reproduce it, thank you. I've added some CHECKs, please let me know if you think this is enough or if I should add more CHECK lines

[fhahn]

Please clean up the IR names here and elsewhere to make the test easier to read, e.g %loop here, drop various epil. prefixes etc

[fhahn]

Simply exit

[fhahn]

Remove

[fhahn]

Try to keep lex ordering (arguably partly broken at the moment but move to correct position)

[fhahn]

LGTM, thanks!

[PietroGhg]

Thanks @fhahn , I don't have commit access, can you merge it for me?