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[PATCH] [Xtensa] Implement FrameLowering methods and stack operation lowering. #92960

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Merged
merged 6 commits into from
Jun 4, 2024
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[PATCH] [Xtensa] Implement FrameLowering methods and stack operation lowering. #92960

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78c9f32
[PATCH] [Xtensa] Implement FrameLowering methods and stack operations…
andreisfr May 22, 2024
c84f7f1
[PATCH] [Xtensa] Minor fixes in FrameLowering and ISelLowering.
andreisfr May 27, 2024
cfe1305
[PATCH] [Xtensa] Check save/restore instructions in emitPrologue and …
andreisfr May 28, 2024
7df895e
[PATCH] [Xtensa] Simplify calle-saved register checking.
andreisfr May 30, 2024
039f075
[PATCH] [Xtensa] Minor changes in callee-saved registers checks
andreisfr May 30, 2024
7a15a99
[PATCH] [Xtensa] Fix compile warnings anf variable name typo.
andreisfr May 30, 2024
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102 changes: 34 additions & 68 deletions llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,70 +33,6 @@ bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const {
MFI.hasVarSizedObjects();
}

#ifndef NDEBUG
/* Check whether instruction I stores some callee-saved register from CSI
*/
static bool checkStoreInstruction(MachineBasicBlock::iterator I,
const std::vector<CalleeSavedInfo> &CSI) {
bool IsStoreInstruction = false;

if (I->getOpcode() == TargetOpcode::COPY) {
Register DstReg = I->getOperand(0).getReg();
Register Reg = I->getOperand(1).getReg();
for (const auto &Info : CSI) {
if (Info.isSpilledToReg()) {
IsStoreInstruction =
(Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
}
if (IsStoreInstruction)
break;
}
} else if (I->getOpcode() == Xtensa::S32I) {
Register Reg = I->getOperand(0).getReg();
for (const auto &Info : CSI) {
if (!Info.isSpilledToReg()) {
IsStoreInstruction = (Info.getReg() == Reg);
}
if (IsStoreInstruction)
break;
}
}

return IsStoreInstruction;
}

/* Check whether instruction I restores some callee-saved register from CSI
*/
static bool checkRestoreInstruction(MachineBasicBlock::iterator I,
const std::vector<CalleeSavedInfo> &CSI) {
bool IsRestoreInstruction = false;

if (I->getOpcode() == TargetOpcode::COPY) {
Register Reg = I->getOperand(0).getReg();
Register DstReg = I->getOperand(1).getReg();
for (const auto &Info : CSI) {
if (Info.isSpilledToReg()) {
IsRestoreInstruction =
(Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
}
if (IsRestoreInstruction)
break;
}
} else if (I->getOpcode() == Xtensa::L32I) {
Register Reg = I->getOperand(0).getReg();
for (const auto &Info : CSI) {
if (!Info.isSpilledToReg()) {
IsRestoreInstruction = (Info.getReg() == Reg);
}
if (IsRestoreInstruction)
break;
}
}

return IsRestoreInstruction;
}
#endif

void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented");
Expand Down Expand Up @@ -136,9 +72,24 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
// instructions are placed at the begin of basic block, so
// iterate over instruction sequence and check that
// save instructions are placed correctly.
for (unsigned i = 0; i < CSI.size(); ++i) {
assert(checkStoreInstruction(MBBI, CSI) &&
for (const auto &Info : CSI) {
int FI = Info.getFrameIdx();
int StoreFI = 0;

#ifndef NDEBUG
// Checking that the instruction is exactly as expected
bool IsStoreInst = false;
if ((MBBI->getOpcode() == TargetOpcode::COPY) && Info.isSpilledToReg()) {
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don't need these braces

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@andreisfr andreisfr May 30, 2024 •
edited
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I corrected "if-condition", is it what you mean? Also, I'm sorry, I changed loop structure a bit with callee-saved register checks to avoid compiler messages like "unused variable" and fix variable name typo. Could you PTAL? Thanks

Register DstReg = MBBI->getOperand(0).getReg();
Register Reg = MBBI->getOperand(1).getReg();
IsStoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
} else {
Register Reg = TII.isStoreToStackSlot(*MBBI, StoreFI);
IsStoreInst = (Reg == Info.getReg()) && (StoreFI == FI);
}
assert(IsStoreInst &&
"Unexpected callee-saved register store instruction");
#endif
++MBBI;
}

Expand Down Expand Up @@ -204,10 +155,25 @@ void XtensaFrameLowering::emitEpilogue(MachineFunction &MF,

// Find the first instruction at the end that restores a callee-saved
// register.
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
for (const auto &Info : CSI) {
int FI = Info.getFrameIdx();
int LoadFI = 0;

--I;
assert(checkRestoreInstruction(I, CSI) &&
#ifndef NDEBUG
// Checking that the instruction is exactly as expected
bool IsRestoreInstr = false;
if (I->getOpcode() == TargetOpcode::COPY) {
Register Reg = I->getOperand(0).getReg();
Register DstReg = I->getOperand(1).getReg();
IsRestoreInstr = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
} else {
Register Reg = TII.isLoadFromStackSlot(*I, LoadFI);
IsRestoreInst = (Info.getReg() == Reg) && (LoadFI == FI);
}
assert(IsRestoreInstr &&
"Unexpected callee-saved register restore instruction");
#endif
}

BuildMI(MBB, I, DL, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP);
Expand Down
24 changes: 24 additions & 0 deletions llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,30 @@ XtensaInstrInfo::XtensaInstrInfo(const XtensaSubtarget &STI)
: XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP),
RI(STI), STI(STI) {}

Register XtensaInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (MI.getOpcode() == Xtensa::L32I) {
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
}
return 0;
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return Register()

}

Register XtensaInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (MI.getOpcode() == Xtensa::S32I) {
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
}
return 0;
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Register()

}

/// Adjust SP by Amount bytes.
void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
MachineBasicBlock &MBB,
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/Xtensa/XtensaInstrInfo.h
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Expand Up @@ -41,6 +41,12 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
// Return the XtensaRegisterInfo, which this class owns.
const XtensaRegisterInfo &getRegisterInfo() const { return RI; }

Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
Expand Down
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