Skip to content

[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets #93481

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Jun 20, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions llvm/include/llvm/IR/RuntimeLibcalls.def
Original file line number Diff line number Diff line change
Expand Up @@ -623,6 +623,7 @@ HANDLE_LIBCALL(RETURN_ADDRESS, nullptr)

// Clear cache
HANDLE_LIBCALL(CLEAR_CACHE, "__clear_cache")
HANDLE_LIBCALL(RISCV_FLUSH_ICACHE, "__riscv_flush_icache")

HANDLE_LIBCALL(UNKNOWN_LIBCALL, nullptr)

25 changes: 25 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -662,6 +662,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,

setBooleanContents(ZeroOrOneBooleanContent);

if (getTargetMachine().getTargetTriple().isOSLinux()) {
// Custom lowering of llvm.clear_cache.
setOperationAction(ISD::CLEAR_CACHE, MVT::Other, Custom);
}

if (Subtarget.hasVInstructions()) {
setBooleanVectorContents(ZeroOrOneBooleanContent);

Expand Down Expand Up @@ -7152,9 +7157,29 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerVPSpliceExperimental(Op, DAG);
case ISD::EXPERIMENTAL_VP_REVERSE:
return lowerVPReverseExperimental(Op, DAG);
case ISD::CLEAR_CACHE: {
assert(getTargetMachine().getTargetTriple().isOSLinux() &&
"llvm.clear_cache only needs custom lower on Linux targets");
SDLoc DL(Op);
SDValue Flags = DAG.getConstant(0, DL, Subtarget.getXLenVT());
return emitFlushICache(DAG, Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2), Flags, DL);
}
}
}

SDValue RISCVTargetLowering::emitFlushICache(SelectionDAG &DAG, SDValue InChain,
SDValue Start, SDValue End,
SDValue Flags, SDLoc DL) const {
MakeLibCallOptions CallOptions;
std::pair<SDValue, SDValue> CallResult =
makeLibCall(DAG, RTLIB::RISCV_FLUSH_ICACHE, MVT::isVoid,
{Start, End, Flags}, CallOptions, DL, InChain);

// This function returns void so only the out chain matters.
return CallResult.second;
}

static SDValue getTargetNode(GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags) {
return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -1037,6 +1037,9 @@ class RISCVTargetLowering : public TargetLowering {
const APInt &AndMask) const override;

unsigned getMinimumJumpTableEntries() const override;

SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
SDValue End, SDValue Flags, SDLoc DL) const;
};

/// As per the spec, the rules for passing vector arguments are as follows:
Expand Down
51 changes: 51 additions & 0 deletions llvm/test/CodeGen/RISCV/clear-cache.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 < %s | FileCheck --check-prefix=RV32 %s
; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefix=RV64 %s
; RUN: llc -mtriple=riscv32-unknown-linux-gnu < %s | FileCheck --check-prefix=RV32-LINUX %s
; RUN: llc -mtriple=riscv64-unknown-linux-gnu < %s | FileCheck --check-prefix=RV64-LINUX %s
; RUN: llc -mtriple=riscv32-unknown-linux-musl < %s | FileCheck --check-prefix=RV32-LINUX %s
; RUN: llc -mtriple=riscv64-unknown-linux-musl < %s | FileCheck --check-prefix=RV64-LINUX %s

declare void @llvm.clear_cache(ptr, ptr)

define void @foo(ptr %a, ptr %b) nounwind {
; RV32-LABEL: foo:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: call __clear_cache
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: foo:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: call __clear_cache
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
;
; RV32-LINUX-LABEL: foo:
; RV32-LINUX: # %bb.0:
; RV32-LINUX-NEXT: addi sp, sp, -16
; RV32-LINUX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-LINUX-NEXT: li a2, 0
; RV32-LINUX-NEXT: call __riscv_flush_icache
; RV32-LINUX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-LINUX-NEXT: addi sp, sp, 16
; RV32-LINUX-NEXT: ret
;
; RV64-LINUX-LABEL: foo:
; RV64-LINUX: # %bb.0:
; RV64-LINUX-NEXT: addi sp, sp, -16
; RV64-LINUX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LINUX-NEXT: li a2, 0
; RV64-LINUX-NEXT: call __riscv_flush_icache
; RV64-LINUX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-LINUX-NEXT: addi sp, sp, 16
; RV64-LINUX-NEXT: ret
call void @llvm.clear_cache(ptr %a, ptr %b)
ret void
}
Loading