-
Notifications
You must be signed in to change notification settings - Fork 13.5k
[SPARC][IAS] Add GNU extension for addc
#94245
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
[SPARC][IAS] Add GNU extension for addc
#94245
Conversation
Created using spr 1.3.4
@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) ChangesTransform Full diff: https://github.com/llvm/llvm-project/pull/94245.diff 2 Files Affected:
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index db4c05cf18062..2b9244519f154 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -560,11 +560,16 @@ def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;
// End of Section A.3
-// or imm, reg, rd -> or reg, imm, rd
-// Nonstandard GNU extension.
-let EmitPriority = 0 in
+
+// Nonstandard GNU extensions.
+let EmitPriority = 0 in {
+ // or imm, reg, rd -> or reg, imm, rd
def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;
+ // addc/addx imm, reg, rd -> or reg, imm, rd
+ def : InstAlias<"addx $simm13, $rs1, $rd", (ADDCri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;
+}
+
// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
// (aka: omit the first arg when it's g0. This is not in the manual, but is
// supported by gnu and solaris as)
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
index 0ca2e50989ca9..b947243f8258f 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -6,6 +6,16 @@
! V9: addx %g2, %g1, %g3 ! encoding: [0x86,0x40,0x80,0x01]
addc %g2, %g1, %g3
+ ! V8: error: invalid instruction mnemonic
+ ! V8-NEXT: addc %g2, 1, %g3
+ ! V9: addx %g2, 1, %g3 ! encoding: [0x86,0x40,0xa0,0x01]
+ addc %g2, 1, %g3
+
+ ! V8: error: invalid instruction mnemonic
+ ! V8-NEXT: addc 1, %g2, %g3
+ ! V9: addx %g2, 1, %g3 ! encoding: [0x86,0x40,0xa0,0x01]
+ addc 1, %g2, %g3
+
! V8: error: invalid instruction mnemonic
! V8-NEXT: addccc %g1, %g2, %g3
! V9: addxcc %g1, %g2, %g3 ! encoding: [0x86,0xc0,0x40,0x02]
|
Note: this PR was created by |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM
Transform `addc imm, %rs, %rd` into `addc %rs, imm, %rd`. This is used in some GNU and Linux code. Reviewers: s-barannikov, rorth, jrtc27, brad0 Reviewed By: s-barannikov Pull Request: llvm#94245 Signed-off-by: Hafidz Muzakky <[email protected]>
def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>; | ||
|
||
// addc/addx imm, reg, rd -> or reg, imm, rd |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
addc/addx imm, reg, rd -> addc/addx reg, imm, rd
?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Oof, my bad~ fixing now.
Fix style errors accidentally introduced in PRs llvm#87259 and llvm#94245. Reviewers: rorth, jrtc27, brad0, s-barannikov Reviewed By: s-barannikov Pull Request: llvm#96019
Transform
addc imm, %rs, %rd
intoaddc %rs, imm, %rd
.This is used in some GNU and Linux code.