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[DAG] computeKnownBits - abs(x) will be zero in the upper bits if x is sign-extended #94382

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Merged
merged 2 commits into from
Jun 5, 2024
Merged

[DAG] computeKnownBits - abs(x) will be zero in the upper bits if x is sign-extended #94382

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be559fe
[X86] combine-abs.ll - add ABS test coverage for #94344
RKSimon Jun 4, 2024
4c7834e
[DAG] computeKnownBits - abs(x) will be zero in the upper bits if x i…
RKSimon Jun 4, 2024
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2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4051,6 +4051,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
case ISD::ABS: {
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known = Known2.abs();
Known.Zero.setHighBits(
ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1) - 1);
break;
}
case ISD::USUBSAT: {
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44 changes: 44 additions & 0 deletions llvm/test/CodeGen/X86/combine-abs.ll
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Expand Up @@ -201,6 +201,50 @@ define <8 x i32> @combine_v8i32_abs_pos(<8 x i32> %a) {
ret <8 x i32> %2
}

; (abs x) upper bits are known zero if x has extra sign bits
define i32 @combine_i32_abs_zerosign(i32 %a) {
; CHECK-LABEL: combine_i32_abs_zerosign:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%1 = ashr i32 %a, 15
%2 = call i32 @llvm.abs.i32(i32 %1, i1 false)
%3 = and i32 %2, -524288 ; 0xFFF80000
ret i32 %3
}

define <8 x i16> @combine_v8i16_abs_zerosign(<8 x i16> %a) {
; SSE-LABEL: combine_v8i16_abs_zerosign:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_v8i16_abs_zerosign:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = ashr <8 x i16> %a, <i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14>
%2 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %1, i1 false)
%3 = and <8 x i16> %2, <i16 32768, i16 32768, i16 32768, i16 32768, i16 32768, i16 32768, i16 32768, i16 32768>
ret <8 x i16> %3
}

; negative test - mask extends beyond known zero bits
define i32 @combine_i32_abs_zerosign_negative(i32 %a) {
; CHECK-LABEL: combine_i32_abs_zerosign_negative:
; CHECK: # %bb.0:
; CHECK-NEXT: sarl $3, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: negl %eax
; CHECK-NEXT: cmovsl %edi, %eax
; CHECK-NEXT: andl $536346624, %eax # imm = 0x1FF80000
; CHECK-NEXT: retq
%1 = ashr i32 %a, 3
%2 = call i32 @llvm.abs.i32(i32 %1, i1 false)
%3 = and i32 %2, -524288 ; 0xFFF80000
ret i32 %3
}

declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1) nounwind readnone
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1) nounwind readnone
declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1) nounwind readnone
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