[clang-format] Handle Verilog delay control

[sstwcw]

I made a mistake when I tried to make the code handle the backtick character like the hash character. The code did not recognize the delay control structure. It caused net names in the declaration to be aligned to the type name instead of the first net name.

new

wire logic #0 mynet, //
              mynet1;

old

wire logic #0 mynet, //
     mynet1;

[llvmbot]

@llvm/pr-subscribers-clang-format

Author: None (sstwcw)

Changes

I made a mistake when I tried to make the code handle the backtick character like the hash character. The code did not recognize the delay control structure. It caused net names in the declaration to be aligned to the type name instead of the first net name.

new

wire logic #<!-- -->0 mynet, //
              mynet1;

old

wire logic #<!-- -->0 mynet, //
     mynet1;

---

Full diff: https://github.com/llvm/llvm-project/pull/95703.diff

2 Files Affected:

• (modified) clang/lib/Format/TokenAnnotator.cpp (+2-1)
• (modified) clang/unittests/Format/FormatTestVerilog.cpp (+9)

diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index 1fe3b61a5a81f..82c101a24a998 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -3410,7 +3410,8 @@ class ExpressionParser {
         } else {
           break;
         }
-      } else if (Tok->is(tok::hash)) {
+      } else if (Tok->is(Keywords.kw_verilogHash)) {
+        // Delay control.
         if (Next->is(tok::l_paren))
           Next = Next->MatchingParen;
         if (Next)
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index b5241a4e0d6ae..fbaf289fbc4d6 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -391,6 +391,15 @@ TEST_F(FormatTestVerilog, Declaration) {
   verifyFormat("wire mynet, mynet1;");
   verifyFormat("wire mynet, //\n"
                "     mynet1;");
+  verifyFormat("wire #0 mynet, mynet1;");
+  verifyFormat("wire logic #0 mynet, mynet1;");
+  verifyFormat("wire #(1, 2, 3) mynet, mynet1;");
+  verifyFormat("wire #0 mynet, //\n"
+               "        mynet1;");
+  verifyFormat("wire logic #0 mynet, //\n"
+               "              mynet1;");
+  verifyFormat("wire #(1, 2, 3) mynet, //\n"
+               "                mynet1;");
   verifyFormat("wire mynet = enable;");
   verifyFormat("wire mynet = enable, mynet1;");
   verifyFormat("wire mynet = enable, //\n"