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AMDGPU: Consolidiate f16 med3 patterns #97399

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Merged
merged 1 commit into from
Jul 2, 2024
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AMDGPU: Consolidiate f16 med3 patterns #97399

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2013,6 +2013,7 @@ def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
AssemblerPredicate<(all_of FeatureVOP3P)>;

def NotHasMed3_16 : Predicate<"!Subtarget->hasMed3_16()">;
def HasMed3_16 : Predicate<"Subtarget->hasMed3_16()">;

def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
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15 changes: 4 additions & 11 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -3534,16 +3534,6 @@ multiclass FPMed3Pat<ValueType vt,
DSTCLAMP.NONE, DSTOMOD.NONE)>;
}

class FP16Med3Pat<ValueType vt,
Instruction med3Inst> : GCNPat<
(fmaxnum_like_nnan (fminnum_like (VOP3Mods vt:$src0, i32:$src0_mods),
(VOP3Mods vt:$src1, i32:$src1_mods)),
(fminnum_like (fmaxnum_like (VOP3Mods vt:$src0, i32:$src0_mods),
(VOP3Mods vt:$src1, i32:$src1_mods)),
(vt (VOP3Mods vt:$src2, i32:$src2_mods)))),
(med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE)
>;

multiclass Int16Med3Pat<Instruction med3Inst,
SDPatternOperator min,
SDPatternOperator max> {
Expand All @@ -3566,6 +3556,10 @@ multiclass Int16Med3Pat<Instruction med3Inst,

defm : FPMed3Pat<f32, V_MED3_F32_e64>;

let SubtargetPredicate = HasMed3_16 in {
defm : FPMed3Pat<f16, V_MED3_F16_e64>;
}

class
IntMinMaxPat<Instruction minmaxInst, SDPatternOperator min_or_max,
SDPatternOperator max_or_min_oneuse> : AMDGPUPat <
Expand Down Expand Up @@ -3611,7 +3605,6 @@ def : FPMinCanonMaxPat<V_MAXMIN_F16_e64, f16, fminnum_like, fmaxnum_like_oneuse>
}

let OtherPredicates = [isGFX9Plus] in {
def : FP16Med3Pat<f16, V_MED3_F16_e64>;
defm : Int16Med3Pat<V_MED3_I16_e64, smin, smax>;
defm : Int16Med3Pat<V_MED3_U16_e64, umin, umax>;
} // End Predicates = [isGFX9Plus]
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