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Enable ICACHE, LPTICKER, TRNG and WATCHDOG for STM32H5 #465

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Enable ICACHE, LPTICKER, TRNG and WATCHDOG for STM32H5 #465

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42 changes: 40 additions & 2 deletions targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
/**
* This file configures the system clock as follows:
*--------------------------------------------------------------------
* System clock source | 1- USE_PLL_HSE_EXTC
* System clock source | 1- USE_PLL_HSE_EXTC
* | 2- USE_PLL_HSE_XTAL
* | 3- USE_PLL_HSI (internal 64 MHz clock)
*--------------------------------------------------------------------
Expand Down Expand Up @@ -45,6 +45,43 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
uint8_t SetSysClock_PLL_HSI(void);
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

/**
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@multiplemonomials multiplemonomials May 25, 2025 •
edited
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system_clock.c feels like the wrong location to put this. Could we create a new .c file for this under TARGET_STM32H5, and then call the function from SystemInit() in TARGET_STM32H5/STM32Cube_FW/system_stm32h5xx.c?

* @brief Enable ICACHE
* @param None
* @retval None
*/

static void EnableICache()
{
MPU_Attributes_InitTypeDef attr;
MPU_Region_InitTypeDef region;

/* Disable MPU before perloading and config update */
HAL_MPU_Disable();

/* Define cacheable memory via MPU */
attr.Number = MPU_ATTRIBUTES_NUMBER5;
attr.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
HAL_MPU_ConfigMemoryAttributes(&attr);

/* BaseAddress-LimitAddress configuration */
region.Enable = MPU_REGION_ENABLE;
region.Number = MPU_REGION_NUMBER5;
region.AttributesIndex = MPU_ATTRIBUTES_NUMBER5;
region.BaseAddress = 0x08FFF800;
region.LimitAddress = 0x08FFFFFF;
region.AccessPermission = MPU_REGION_ALL_RW;
region.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
region.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
HAL_MPU_ConfigRegion(&region);

/* Enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

/* Enable ICACHE */
HAL_ICACHE_Enable();
}

/**
* @brief Configures the System clock source
* @note This function should be called only once the RCC clock configuration
Expand Down Expand Up @@ -74,6 +111,7 @@ void SetSysClock(void)
}
}
}
EnableICache();
}


Expand Down Expand Up @@ -108,7 +146,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
#endif
if(HSE_VALUE % 2000000 == 0)
{
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000; // Divide down input clock to 2MHz
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000; // Divide down input clock to 2MHz
RCC_OscInitStruct.PLL.PLLN = 250; // Multiply up to 500MHz VCO clock
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
}
Expand Down
2 changes: 1 addition & 1 deletion targets/TARGET_STM/lp_ticker.c
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Expand Up @@ -266,7 +266,7 @@ void lp_ticker_init(void)
#if defined (LPTIM_ACTIVEEDGE_FALLING)
LptimHandle.Init.Trigger.ActiveEdge = LPTIM_ACTIVEEDGE_FALLING;
#endif
#if defined(TARGET_STM32U5) || defined(TARGET_STM32U0)
#if defined(TARGET_STM32U5) || defined(TARGET_STM32H5) || defined(TARGET_STM32U0)
LptimHandle.Init.Period = 0xFFFF;
#endif
#if defined (LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION)
Expand Down
2 changes: 1 addition & 1 deletion targets/TARGET_STM/trng_api.c
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Expand Up @@ -88,7 +88,7 @@ void trng_init(trng_t *obj)
}
}

#elif defined(TARGET_STM32G4) || defined(TARGET_STM32U0)
#elif defined(TARGET_STM32G4) || defined(TARGET_STM32H5) || defined(TARGET_STM32U0)
/* RNG and USB clocks have the same HSI48 source which has been enabled in SetSysClock */
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;

Expand Down
2 changes: 1 addition & 1 deletion targets/TARGET_STM/watchdog_api.c
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Expand Up @@ -137,7 +137,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void)
features.clock_max_frequency = 47000;
#elif defined(STM32F0) || defined(STM32F3)
features.clock_max_frequency = 50000;
#elif defined(STM32H7) || defined(STM32L4) || defined(STM32U5)
#elif defined(STM32H7) || defined(STM32L4) || defined(STM32U5) || defined(STM32H5)
features.clock_max_frequency = 33600;
#elif defined(STM32G0) || defined(STM32L5) || defined(STM32G4) || defined(STM32WB) || defined(STM32WL) || defined(STM32U0)
features.clock_max_frequency = 34000;
Expand Down
15 changes: 7 additions & 8 deletions targets/targets.json5
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Expand Up @@ -3060,7 +3060,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
"STM32G4A1xx"
]
},

// STM32H5 Targets -------------------------------------------------------------------------------------------------
"MCU_STM32H5": {
"inherits": [
Expand Down Expand Up @@ -3104,14 +3104,13 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
"device_has_add": [
"MPU",
"ANALOGOUT",
"SPI_32BIT_WORDS"
"SPI_32BIT_WORDS",
"TRNG"
],
"device_has_remove": [
"FLASH",
"LPTICKER",
"CAN",
"SERIAL_FC",
"WATCHDOG"
"SERIAL_FC"
],
"is_mcu_family_target": true
},
Expand Down Expand Up @@ -3193,7 +3192,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
"device_name": "STM32H563ZITx",
"image_url": "https://www.st.com/bin/ecommerce/api/image.PF274337.en.feature-description-include-personalized-no-cpn-medium.jpg"
},

// STM32H7 Targets -------------------------------------------------------------------------------------------------
"MCU_STM32H7": {
"inherits": [
Expand Down Expand Up @@ -3435,7 +3434,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
],
"device_name": "STM32H745ZITx"
},

// These targets contain the extra bits to add to the MCU_STM32H745xI target to set it for the
// CM4 or CM7 core.
"MCU_STM32H745xI_CM4": {
Expand Down Expand Up @@ -4894,7 +4893,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
],
"image_url": "https://www.st.com/bin/ecommerce/api/image.PF273876.en.feature-description-include-personalized-no-cpn-large.jpg"
},

// STM32U5 Targets -------------------------------------------------------------------------------------------------
"MCU_STM32U5": {
"inherits": [
Expand Down