FPGA: Add `fpga_template` sample #1262

whitepau · 2022-12-12T15:19:47Z

Adding a New Sample(s)

Description

Add code sample for template FPGA CMake design.

Checklist

Administrative

Review sample design with the appropriate Domain Expert:
[ N/A ] If you have any new dependencies/binaries, inform the oneAPI Code Samples Project Manager

Code Development

Implement coding guidelines and ensure code quality. see wiki for details
Adhere to readme template
Enforce format via clang-format config file
Adhere to sample.json specification. https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-specification
Ensure/create CI test configurations for sample (ciTests field) https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-ci-test-object
Run jsonlint on sample.json to verify json syntax. www.jsonlint.com

Security and Legal

OSPDT Approval (see Project Manager for assistance)
Compile using the following compiler flags and fix any warnings, the falgs are: "/Wall -Wformat-security -Werror=format-security"
[ N/A ] Bandit Scans (Python only)
Virus scan

Review

Review DPC++ code with Paul Peterseon. (GitHub User: pmpeter1)
Review readme with Tom Lenth(@tomlenth) and/or Project Manager
Tested using Dev Cloud when applicable

…ject file" This reverts commit 98a0dfc.

yuguen · 2022-12-12T16:30:25Z

@tomlenth and @pmpeter1: This PR will not be merged in the master branch but will be reopened to the development branch when available.

Please review this new sample for it to be ready when the development branch opens, thanks!

DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md

…I-samples into add-fpga_template

...Programming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt

yuguen · 2023-01-06T10:06:41Z

This new sample should now be moved to the C++SYCL_FPGA folder

whitepau

resolve open comments

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md

…emplate/README.md formatting Co-authored-by: yuguen-intel <[email protected]>

yuguen · 2023-01-26T13:54:06Z

Please incorporate these changes in your PR: #1307

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

pmpeter1 · 2023-01-27T15:58:38Z

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

+    auto selector = sycl::ext::intel::fpga_emulator_selector{};
+#endif
+#else
+    assert(false) && "this design requires oneAPI 2023.0 or 2023.1!"


Doesn't the older style also work with pre-2023 releases? What is they user is still using 2022, would it fail?

The older style also works for older releases, but users with older releases such as 2022.2 are expected to fetch the 2022.2 tag of the code samples, which won't include this sample (as it uses features of the compiler that did not exist then).
Why is this sample doing this special handling for 2023.0 and 2023.1?
-> Paul wants to distribute this sample to selected customers who have the 2023.0 version of the compiler (a.k.a. not wait until the 2023.1 version of the compiler is out)
-> The 2023.1 version of the compiler needs the new selectors.

So this approach is temporary: until we get close to the 2023.1 release. Once we are a few weeks away from the release, we'll remove the logic for handling the 2023.0 case, it will then only contain the new selectors, as expected for the 2023.1 release.

Having the #ifdef is OK to be flexible. My point was that users don't always limit the code and toolkit combinations to what we assume they should, so being defensive and broader in what is supported is usually better.

None of the code samples will work with a previous version of the compiler due to headers being modified etc.
So we are not trying to get full compatibility here, just the two cases we are interested in.
We expect the users to read the top level readme which starts by stating that they should fetch the appropriate version of the samples that matches their compiler version

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

pmpeter1 · 2023-01-27T16:01:29Z

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

+      int a_val = a_in[idx];
+      int b_val = b_in[idx];
+      int sum = a_val + b_val;
+      c_out[idx] = sum;


Why be more verbose here. This is equivalent to

c_out[idx] = a_in[idx] + b_in[idx];

This is not that long or complex so why do we need the extra temporaries the compiler will just need to optimize out. Is this needed as part of an explanation of how the compiler works internally?

I can see how this appears at odds with my earlier-stated desire for conciseness :)

I included this verbosity to be consistent with an update to the fpga_compile code sample that we are also working on. Separating out the instructions like this makes it easier to identify them in the FPGA reports. The one-liner will result in two Memory Load instructions, a Memory Store instruction and an Add instruction all mapping to the same line of code, whereas by splitting them up like this, the user can clearly see how each line of code maps to some hardware in the design.

OK, so you are doing this explicitly to demonstrate how to make the FPGA reports more readable.

whitepau

address @pmpeter1's comments

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

whitepau · 2023-02-01T16:01:06Z

Please incorporate these changes in your PR: #1307

Done

pmpeter1 · 2023-02-01T20:44:37Z

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

+      int a_val = a_in[idx];
+      int b_val = b_in[idx];
+      int sum = a_val + b_val;
+      c_out[idx] = sum;


OK, so you are doing this explicitly to demonstrate how to make the FPGA reports more readable.

pmpeter1 · 2023-02-01T20:46:24Z

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

+    auto selector = sycl::ext::intel::fpga_emulator_selector{};
+#endif
+#else
+    assert(false) && "this design requires oneAPI 2023.0 or 2023.1!"


Having the #ifdef is OK to be flexible. My point was that users don't always limit the code and toolkit combinations to what we assume they should, so being defensive and broader in what is supported is usually better.

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

pmpeter1 · 2023-02-03T16:26:21Z

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

+class VectorAddID;
+
+struct VectorAdd {
+ public:


public: is redundant in a struct

@jkinsky

* FPGA: Update dsp_control README (#1269) * FPGA: Revert "FPGA: Remove db query 9 in 2023.0 (#1257)" (#1281) This reverts commit 86c4aa8 and reenables the db9 code sample in 2023.1 * FPGA: Batch PR - sim support - selectors update - readme rework (#1280) This PR: - adds simulation support to almost all of the remaining FPGA code samples - reworks all the FPGA code sample READMEs to update the software requirements - reworks the FPGA code samples READMEs from the Tutorials folder to now reference the FPGA top-level README and remove any duplicated information - changes all FPGA samples selectors to comply with the 2023.1 new selectors - edits all FPGA READMEs to specify to use the CL_CONTEXT_MPSIM_DEVICE_INTELFPGA environment variable when running the FPGA simulator flow * FPGA: Remove all references to Windows in README (#1273) * Update samples to SYCL 2023 specifications (#1286) * FPGA: fix io_streaming assets location (#1289) * FPGA: remove instructions to build merge_sort on Windows (#1290) * FPGA: Update printf readme and fixed some typos (#1288) * Added simulation instructions to README for 2023.1 * Corrected for running simulation since windows need multiple commmands to run * FPGA: Top level readme update (#1285) * removed dpc_common.hpp dependency (#1282) Co-authored-by: Rakshith Krishnappa <[email protected]> * FPGA: add simulation support to the private_copies samples (#1296) * Reverted PR#1265 and PR#1266 (#1298) * Update repo Readme.md (#1308) Update readme to reflect the current changes in repo behavior, which is that the master branch is stable and works with current released toolkits. * FPGA: Move all FPGA samples to IP Authoring, targeting Agilex by default (#1307) # Existing Sample Changes ## Description All of the FPGA samples are moved to the IP Authoring flow. The default target for all samples is now Agilex. For targeting a specific board, the user must run `cmake` with `-DFPGA_DEVICE=` his own BSP name. * matrix_mul_mkl: use single precision for compatibility with all devices (#1310) * updated latest GPU devices in Occupancy Calculator (#1309) * FPGA: add a warning when compiling the CRR design in the simulation flow (#1318) The simulation runtime of the CRR design is very long. This PR adds a message that the users can see when they compile for simulation warning them about this long runtime. * FPGA: Update throughput numbers for mvdr_beamforming design for 2023.1 release (#1325) * FPGA: Update QRD s10 default seed (#1324) This PR updates the PAC S10 default seed of the QRD design in order to meet the expected performance for 2023.1 * FPGA: Add `device_global` sample (#1291) * update the sample with mcg59 as a default engine (#1331) * FPGA: remove fp-relaxed from compile cli, use fp-precise for widnows emulator (#1321) * FPGA: create new invocation interfaces sample (#1303) * FPGA: New Code Sample `minimum_latency` (#1302) * FPGA: Fix typo (#1342) * FPGA: Add `fpga_template` sample (#1262) * FPGA: Bug fix to the functionality of the `dynamic_profiler` tutorial (#1340) * FPGA: Reduce the `decompress` test file sizes when running simulation to make the runtime faster (#1351) * Compilator update (#1349) * Change compiler in makefiles * Change compiler in cmake files * Updated TBB source files to use default_selector_v (#1360) Co-authored-by: gta <[email protected]> * update Makefile to compile with icpx (#1363) Co-authored-by: rupakroyintel <[email protected]> * FPGA: Typo for s10 support in `device_globals` (#1359) * FPGA: Add platform designer tutorial (#1348) * FPGA: prevent an out of bounds memory access in streaming_qrd.hpp (#1367) * FPGA: Move the simple-add and vector-add samples to the IP Authoring flow (#1369) * FPGA: Update onchip memory cache readme (#1358) Updated readme to match new template (with exceptions for FPGA), updated branding, updated some formatting, corrected some grammar. Updated content to reflect changes requested by reviewer. * FPGA: Remove Windows simulator command for memory_attributes (#1374) * Fix compilation error (#1371) * FPGA: replace Agilex™ with Agilex® (#1372) * FPGA: Fix decompress emulation flow not using the correct files(#1373) * FPGA: Fix race condition in the buffered_host_streaming sample (#1375) * Update FPGA optimize inner loop readme (#1380) Restructure to match new template. Updated formatting. Rewrote and restructured for clarity. Moved images to assets folder. Corrected some relative link issues (assuming master branch). * FPGA: incorrect path update (#1382) * Relax correctness test for Ch04 matrix multiply (#1378) Co-authored-by: gta <[email protected]> * FPGA: Reduce the design size of the memory_attributes design in simulation (#1383) * FPGA: Fix inconsistent device flags in 4 samples (#1384) Some of the samples required the device flags to be set using -DDEVICE_FLAG=-DAgilex rather than -DDEVICE_FLAG=Agilex. This change makes all the samples consistent with the second option. * FPGA Shannonization Sample readme update (#1386) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Added missing build and run instructions for Windows. Rewrote and restructured some sections for clarity. * FPGA: Update Host-Device Streaming using USM readme (#1391) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected some formatting. Rewrote and restructured some sections for clarity. * Update FPGA pipe array readme (#1385) Changed the sample name in the readme to match the name in the sample.json file. Restructured the readme to match the new template, with exceptions related to FPGA structure. Corrected formatting. Updated some branding. Rewrote and restructured some sections for clarity. * Revert "FPGA: Remove Windows simulator command for memory_attributes (#1374)" (#1389) This reverts commit 149dbb6. * FPGA: better fix for the concurrency issue in buffered_host_streaming (#1392) * FPGA: Reduce test size from 64 to 2 for memory_attributes simulator target (#1390) * FPGA: update gzip seed (#1381) * FPGA: improve build instructions in the READMEs for samples that require IS_BSP (#1388) * FPGA: make the decompress design use shared memory allocations in IPA flow (#1396) * FPGA: check USM support in fpga_template (#1397) * FPGA: Add the missing simulator selector to the CRR design. (#1398) * ApplicationDebugger: rely on ONEAPI_DEVICE_SELECTOR to select device. (#1387) Affected samples: array-transform, jacobi. Remove the custom selector.hpp files. Update README to use ONEAPI_DEVICE_SELECTOR instead of arguments. Update sample.json files. Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: improve the minimum_latency cmake device detection (#1399) * Triangular Loop readme update (#1393) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Corrected some formatting. Rewrote and restructured some sections for clarity. * Zero Copy Data Transfer readme update (#1394) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Rewrote and restructured some sections for clarity. * FPGA: Improve the `fpga_compile` tutorial (#1347) * FPGA: Add platform designer tutorial: Readme clarification (#1400) * FPGA compile update - fix compile problem with USM device check (#1402) * FPGA: compile - remove +/- in path (#1404) * Document that simulator for mvdr_beamforming can take a long time (#1405) * FPGA: Add note to large designs READMEs to warn users about large FPGA parts requirements (#1407) * changed the default sub-group size to 32 (#1406) Co-authored-by: Praveen Kundurthy <[email protected]> * FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414) * FPGA: Reduce test size for simple_host_streaming simulator target (#1415) * ApplicationDebugger: update make targets with ONEAPI_DEVICE_SELECTOR (#1416) Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: fix anr cmake file (#1420) The anr sample cmake file was not allowing to target parts that did not contain the keywords "agilex" or "a10" or "s10". This PR addresses this gap. * Added release.json for samples CI (#1418) * FPGA: add include path in compile command (#1423) * FPGA: fix the HW compile seed for the ivdep sample (#1427) This sample is notorious for getting a high percentage of timing failures during quartus compiles on the PAC boards. This PR fixes the seed so that we know it compiles cleanly on PAC boards. * updated GPU Occupancy Calculator with PVC GPU (#1425) * updated GPU Occupancy Calculator with PVC GPU * updated GPU names in Occupancy Calculator * Tools/ApplicationDebugger: update jacobi sample. (#1421) * Restructure the source code: - the common parts are moved to jacobi.cpp; - the computation parts have two flavors: - bugged.cpp contains computation with bugs; - fixed.cpp contains fixed computation; * Simplify reductions; * Update README. Signed-off-by: Saiapova, Natalia <[email protected]> * Update GPU-Opt-Guide examples to 2023.03.14 (#1432) * FPGA: Provide smaller input file size option for gzip (#1431) Provide the option to run gzip_ll with 100 B file so that the simulator flow takes < 2h to finish for Questa FSE. * updated oneapi_essentials module2 notebook and code sample (#1430) * updated oneapi_essentials module2 notebook and code sample * updated Makefile * Add all files (#1437) * Add all files (#1436) * Updated sample.json files for cuBLAS and matrix_mul_SYCLMigration (#1442) * change compiler for new oneDNN release (#1435) * adding Jupyter Notebooks for cuda to sycl migration learning path (#1439) * FPGA: Reduce array size for simulation in the loop_unroll sample (#1443) The loop unroll code sample's array size was 1024 for simulation which caused simulating with Questa FSE on Windows to be very slow (>24 hours). This changes the array size to 16 which lets the simulation to complete in ~1 hour using Questa FSE on Windows. * FPGA: fix incorrect paths in Windows CI steps (#1445) Some FPGA samples had incorrect path in their CI steps in the sample.json file. * Pred modeling updates (#1446) * Predictive Modeling Updates * fix complete --------- Co-authored-by: u51369 <[email protected]> * Rendering: path tracing with embree cpu updates (#1362) * First pass at CPU Embree 4 changes, need to change header Signed-off-by: Carroll, Michael R <[email protected]> * Added embree 4 headers and CMake flexibility Signed-off-by: Carroll, Michael R <[email protected]> * warning fixes for boolean Signed-off-by: Carroll, Michael R <[email protected]> * README, coherent ray updates for embree 4 Signed-off-by: Carroll, Michael R <[email protected]> * style formatting Signed-off-by: Carroll, Michael R <[email protected]> * README fixes and removal of stub mis code Signed-off-by: Carroll, Michael R <[email protected]> * Updating sample.json for dirs and ONSAM-1563 Signed-off-by: Carroll, Michael R <[email protected]> * sample.json for MacOS per ONSAM ticket Signed-off-by: Carroll, Michael R <[email protected]> * pathtracer lib ref update for macos validation consistency Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering: IntroToRayTracingWithEmbree embree4 update (#1354) * rkRayTracer Embree4 GPU: Updated sample.json for validation Signed-off-by: Carroll, Michael R <[email protected]> * Embree 4 compatibility updates for Ray Tracer Signed-off-by: Carroll, Michael R <[email protected]> * Ray Tracer Embree4 sample.json update Signed-off-by: Carroll, Michael R <[email protected]> * Firmer reference to rkcommon (macOS validation helper) Signed-off-by: Carroll, Michael R <[email protected]> * Cleaning up helper script/CMake syntax Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering Embree4 GSG Updates (#1353) * stage embree gsg for cpu Signed-off-by: MichaelRoyceCarroll <[email protected]> * Add gpu to Rendering 02_embree... TODO: test/json val/readme Signed-off-by: Carroll, Michael R <[email protected]> * Adding license file in all folders for 02_embree Signed-off-by: Carroll, Michael R <[email protected]> * Update Embree gsg README.md * Update embree4 readme.md * embree minimal samples updated for embree 4... prewindows testing Signed-off-by: Carroll, Michael R <[email protected]> * Checked on Windows, fixed readme... ready for PR review Signed-off-by: MichaelRoyceCarroll <[email protected]> * Embree4 gsg JSON automation updates Signed-off-by: Carroll, Michael R <[email protected]> * README updates... thx to @jkinsky feedback Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> * Fix double to float (#1447) * FPGA: Platform designer readme touchup (#1449) * Added SECURITY.md (#1450) * Removed Windows validation step from ciTests (#1451) * Rtk development branch fix for validation 20230320 (#1458) * sample.json update for macos validation workaround Signed-off-by: Carroll, Michael R <[email protected]> * samples.json workaround for validation rtk pathtracer Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * FPGA: Fix windows CI steps in platform designer (#1459) * Updated Makefile.win to resolve Windows compilation errors (#1460) * Updated makefile to remove sycl.lib (#1468) * Allow Ch18 DPC++ book code samples to compile (#1467) * Uncommented CMakeLists.txt for Ch18 DPC++ book code samples * Updated CMakeLists.txt * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json (#1470) * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json Signed-off-by: Natalia Saiapova <[email protected]> * Update sample.json --------- Signed-off-by: Natalia Saiapova <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> * FPGA: document RTL library issue with the 2023.1 release. (#1471) (#1472) * FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476) This is a port of #1474 * FPGA: reduce snappy decompression simulation duration (#1478) When using Questa FSE, the simulation time of the snappy decompression of Stratix 10 was excessively long, This PR reduces the problem size when running in simulation to speed up the execution time. This PR is a port of #1475. * FPGA: Set fp model to "precise" for ac_fixed sample (#1483) * set fp-model to precise for emu only * set fp-model to precise for all platforms --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]>

@jkinsky

* 2023.1 Release PR (#1499) * FPGA: Update dsp_control README (#1269) * FPGA: Revert "FPGA: Remove db query 9 in 2023.0 (#1257)" (#1281) This reverts commit 86c4aa8 and reenables the db9 code sample in 2023.1 * FPGA: Batch PR - sim support - selectors update - readme rework (#1280) This PR: - adds simulation support to almost all of the remaining FPGA code samples - reworks all the FPGA code sample READMEs to update the software requirements - reworks the FPGA code samples READMEs from the Tutorials folder to now reference the FPGA top-level README and remove any duplicated information - changes all FPGA samples selectors to comply with the 2023.1 new selectors - edits all FPGA READMEs to specify to use the CL_CONTEXT_MPSIM_DEVICE_INTELFPGA environment variable when running the FPGA simulator flow * FPGA: Remove all references to Windows in README (#1273) * Update samples to SYCL 2023 specifications (#1286) * FPGA: fix io_streaming assets location (#1289) * FPGA: remove instructions to build merge_sort on Windows (#1290) * FPGA: Update printf readme and fixed some typos (#1288) * Added simulation instructions to README for 2023.1 * Corrected for running simulation since windows need multiple commmands to run * FPGA: Top level readme update (#1285) * removed dpc_common.hpp dependency (#1282) Co-authored-by: Rakshith Krishnappa <[email protected]> * FPGA: add simulation support to the private_copies samples (#1296) * Reverted PR#1265 and PR#1266 (#1298) * Update repo Readme.md (#1308) Update readme to reflect the current changes in repo behavior, which is that the master branch is stable and works with current released toolkits. * FPGA: Move all FPGA samples to IP Authoring, targeting Agilex by default (#1307) # Existing Sample Changes ## Description All of the FPGA samples are moved to the IP Authoring flow. The default target for all samples is now Agilex. For targeting a specific board, the user must run `cmake` with `-DFPGA_DEVICE=` his own BSP name. * matrix_mul_mkl: use single precision for compatibility with all devices (#1310) * updated latest GPU devices in Occupancy Calculator (#1309) * FPGA: add a warning when compiling the CRR design in the simulation flow (#1318) The simulation runtime of the CRR design is very long. This PR adds a message that the users can see when they compile for simulation warning them about this long runtime. * FPGA: Update throughput numbers for mvdr_beamforming design for 2023.1 release (#1325) * FPGA: Update QRD s10 default seed (#1324) This PR updates the PAC S10 default seed of the QRD design in order to meet the expected performance for 2023.1 * FPGA: Add `device_global` sample (#1291) * update the sample with mcg59 as a default engine (#1331) * FPGA: remove fp-relaxed from compile cli, use fp-precise for widnows emulator (#1321) * FPGA: create new invocation interfaces sample (#1303) * FPGA: New Code Sample `minimum_latency` (#1302) * FPGA: Fix typo (#1342) * FPGA: Add `fpga_template` sample (#1262) * FPGA: Bug fix to the functionality of the `dynamic_profiler` tutorial (#1340) * FPGA: Reduce the `decompress` test file sizes when running simulation to make the runtime faster (#1351) * Compilator update (#1349) * Change compiler in makefiles * Change compiler in cmake files * Updated TBB source files to use default_selector_v (#1360) Co-authored-by: gta <[email protected]> * update Makefile to compile with icpx (#1363) Co-authored-by: rupakroyintel <[email protected]> * FPGA: Typo for s10 support in `device_globals` (#1359) * FPGA: Add platform designer tutorial (#1348) * FPGA: prevent an out of bounds memory access in streaming_qrd.hpp (#1367) * FPGA: Move the simple-add and vector-add samples to the IP Authoring flow (#1369) * FPGA: Update onchip memory cache readme (#1358) Updated readme to match new template (with exceptions for FPGA), updated branding, updated some formatting, corrected some grammar. Updated content to reflect changes requested by reviewer. * FPGA: Remove Windows simulator command for memory_attributes (#1374) * Fix compilation error (#1371) * FPGA: replace Agilex™ with Agilex® (#1372) * FPGA: Fix decompress emulation flow not using the correct files(#1373) * FPGA: Fix race condition in the buffered_host_streaming sample (#1375) * Update FPGA optimize inner loop readme (#1380) Restructure to match new template. Updated formatting. Rewrote and restructured for clarity. Moved images to assets folder. Corrected some relative link issues (assuming master branch). * FPGA: incorrect path update (#1382) * Relax correctness test for Ch04 matrix multiply (#1378) Co-authored-by: gta <[email protected]> * FPGA: Reduce the design size of the memory_attributes design in simulation (#1383) * FPGA: Fix inconsistent device flags in 4 samples (#1384) Some of the samples required the device flags to be set using -DDEVICE_FLAG=-DAgilex rather than -DDEVICE_FLAG=Agilex. This change makes all the samples consistent with the second option. * FPGA Shannonization Sample readme update (#1386) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Added missing build and run instructions for Windows. Rewrote and restructured some sections for clarity. * FPGA: Update Host-Device Streaming using USM readme (#1391) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected some formatting. Rewrote and restructured some sections for clarity. * Update FPGA pipe array readme (#1385) Changed the sample name in the readme to match the name in the sample.json file. Restructured the readme to match the new template, with exceptions related to FPGA structure. Corrected formatting. Updated some branding. Rewrote and restructured some sections for clarity. * Revert "FPGA: Remove Windows simulator command for memory_attributes (#1374)" (#1389) This reverts commit 149dbb6. * FPGA: better fix for the concurrency issue in buffered_host_streaming (#1392) * FPGA: Reduce test size from 64 to 2 for memory_attributes simulator target (#1390) * FPGA: update gzip seed (#1381) * FPGA: improve build instructions in the READMEs for samples that require IS_BSP (#1388) * FPGA: make the decompress design use shared memory allocations in IPA flow (#1396) * FPGA: check USM support in fpga_template (#1397) * FPGA: Add the missing simulator selector to the CRR design. (#1398) * ApplicationDebugger: rely on ONEAPI_DEVICE_SELECTOR to select device. (#1387) Affected samples: array-transform, jacobi. Remove the custom selector.hpp files. Update README to use ONEAPI_DEVICE_SELECTOR instead of arguments. Update sample.json files. Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: improve the minimum_latency cmake device detection (#1399) * Triangular Loop readme update (#1393) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Corrected some formatting. Rewrote and restructured some sections for clarity. * Zero Copy Data Transfer readme update (#1394) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Rewrote and restructured some sections for clarity. * FPGA: Improve the `fpga_compile` tutorial (#1347) * FPGA: Add platform designer tutorial: Readme clarification (#1400) * FPGA compile update - fix compile problem with USM device check (#1402) * FPGA: compile - remove +/- in path (#1404) * Document that simulator for mvdr_beamforming can take a long time (#1405) * FPGA: Add note to large designs READMEs to warn users about large FPGA parts requirements (#1407) * changed the default sub-group size to 32 (#1406) Co-authored-by: Praveen Kundurthy <[email protected]> * FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414) * FPGA: Reduce test size for simple_host_streaming simulator target (#1415) * ApplicationDebugger: update make targets with ONEAPI_DEVICE_SELECTOR (#1416) Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: fix anr cmake file (#1420) The anr sample cmake file was not allowing to target parts that did not contain the keywords "agilex" or "a10" or "s10". This PR addresses this gap. * Added release.json for samples CI (#1418) * FPGA: add include path in compile command (#1423) * FPGA: fix the HW compile seed for the ivdep sample (#1427) This sample is notorious for getting a high percentage of timing failures during quartus compiles on the PAC boards. This PR fixes the seed so that we know it compiles cleanly on PAC boards. * updated GPU Occupancy Calculator with PVC GPU (#1425) * updated GPU Occupancy Calculator with PVC GPU * updated GPU names in Occupancy Calculator * Tools/ApplicationDebugger: update jacobi sample. (#1421) * Restructure the source code: - the common parts are moved to jacobi.cpp; - the computation parts have two flavors: - bugged.cpp contains computation with bugs; - fixed.cpp contains fixed computation; * Simplify reductions; * Update README. Signed-off-by: Saiapova, Natalia <[email protected]> * Update GPU-Opt-Guide examples to 2023.03.14 (#1432) * FPGA: Provide smaller input file size option for gzip (#1431) Provide the option to run gzip_ll with 100 B file so that the simulator flow takes < 2h to finish for Questa FSE. * updated oneapi_essentials module2 notebook and code sample (#1430) * updated oneapi_essentials module2 notebook and code sample * updated Makefile * Add all files (#1437) * Add all files (#1436) * Updated sample.json files for cuBLAS and matrix_mul_SYCLMigration (#1442) * change compiler for new oneDNN release (#1435) * adding Jupyter Notebooks for cuda to sycl migration learning path (#1439) * FPGA: Reduce array size for simulation in the loop_unroll sample (#1443) The loop unroll code sample's array size was 1024 for simulation which caused simulating with Questa FSE on Windows to be very slow (>24 hours). This changes the array size to 16 which lets the simulation to complete in ~1 hour using Questa FSE on Windows. * FPGA: fix incorrect paths in Windows CI steps (#1445) Some FPGA samples had incorrect path in their CI steps in the sample.json file. * Pred modeling updates (#1446) * Predictive Modeling Updates * fix complete --------- Co-authored-by: u51369 <[email protected]> * Rendering: path tracing with embree cpu updates (#1362) * First pass at CPU Embree 4 changes, need to change header Signed-off-by: Carroll, Michael R <[email protected]> * Added embree 4 headers and CMake flexibility Signed-off-by: Carroll, Michael R <[email protected]> * warning fixes for boolean Signed-off-by: Carroll, Michael R <[email protected]> * README, coherent ray updates for embree 4 Signed-off-by: Carroll, Michael R <[email protected]> * style formatting Signed-off-by: Carroll, Michael R <[email protected]> * README fixes and removal of stub mis code Signed-off-by: Carroll, Michael R <[email protected]> * Updating sample.json for dirs and ONSAM-1563 Signed-off-by: Carroll, Michael R <[email protected]> * sample.json for MacOS per ONSAM ticket Signed-off-by: Carroll, Michael R <[email protected]> * pathtracer lib ref update for macos validation consistency Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering: IntroToRayTracingWithEmbree embree4 update (#1354) * rkRayTracer Embree4 GPU: Updated sample.json for validation Signed-off-by: Carroll, Michael R <[email protected]> * Embree 4 compatibility updates for Ray Tracer Signed-off-by: Carroll, Michael R <[email protected]> * Ray Tracer Embree4 sample.json update Signed-off-by: Carroll, Michael R <[email protected]> * Firmer reference to rkcommon (macOS validation helper) Signed-off-by: Carroll, Michael R <[email protected]> * Cleaning up helper script/CMake syntax Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering Embree4 GSG Updates (#1353) * stage embree gsg for cpu Signed-off-by: MichaelRoyceCarroll <[email protected]> * Add gpu to Rendering 02_embree... TODO: test/json val/readme Signed-off-by: Carroll, Michael R <[email protected]> * Adding license file in all folders for 02_embree Signed-off-by: Carroll, Michael R <[email protected]> * Update Embree gsg README.md * Update embree4 readme.md * embree minimal samples updated for embree 4... prewindows testing Signed-off-by: Carroll, Michael R <[email protected]> * Checked on Windows, fixed readme... ready for PR review Signed-off-by: MichaelRoyceCarroll <[email protected]> * Embree4 gsg JSON automation updates Signed-off-by: Carroll, Michael R <[email protected]> * README updates... thx to @jkinsky feedback Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> * Fix double to float (#1447) * FPGA: Platform designer readme touchup (#1449) * Added SECURITY.md (#1450) * Removed Windows validation step from ciTests (#1451) * Rtk development branch fix for validation 20230320 (#1458) * sample.json update for macos validation workaround Signed-off-by: Carroll, Michael R <[email protected]> * samples.json workaround for validation rtk pathtracer Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * FPGA: Fix windows CI steps in platform designer (#1459) * Updated Makefile.win to resolve Windows compilation errors (#1460) * Updated makefile to remove sycl.lib (#1468) * Allow Ch18 DPC++ book code samples to compile (#1467) * Uncommented CMakeLists.txt for Ch18 DPC++ book code samples * Updated CMakeLists.txt * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json (#1470) * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json Signed-off-by: Natalia Saiapova <[email protected]> * Update sample.json --------- Signed-off-by: Natalia Saiapova <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> * FPGA: document RTL library issue with the 2023.1 release. (#1471) (#1472) * FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476) This is a port of #1474 * FPGA: reduce snappy decompression simulation duration (#1478) When using Questa FSE, the simulation time of the snappy decompression of Stratix 10 was excessively long, This PR reduces the problem size when running in simulation to speed up the execution time. This PR is a port of #1475. * FPGA: Set fp model to "precise" for ac_fixed sample (#1483) * set fp-model to precise for emu only * set fp-model to precise for all platforms --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]> * test oneapi ci job master -> gh-pages. Signed-off-by: michael vincerra <[email protected]> --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: michael vincerra <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]>

@jkinsky

* 2023.1 Release PR (#1499) * FPGA: Update dsp_control README (#1269) * FPGA: Revert "FPGA: Remove db query 9 in 2023.0 (#1257)" (#1281) This reverts commit 86c4aa8 and reenables the db9 code sample in 2023.1 * FPGA: Batch PR - sim support - selectors update - readme rework (#1280) This PR: - adds simulation support to almost all of the remaining FPGA code samples - reworks all the FPGA code sample READMEs to update the software requirements - reworks the FPGA code samples READMEs from the Tutorials folder to now reference the FPGA top-level README and remove any duplicated information - changes all FPGA samples selectors to comply with the 2023.1 new selectors - edits all FPGA READMEs to specify to use the CL_CONTEXT_MPSIM_DEVICE_INTELFPGA environment variable when running the FPGA simulator flow * FPGA: Remove all references to Windows in README (#1273) * Update samples to SYCL 2023 specifications (#1286) * FPGA: fix io_streaming assets location (#1289) * FPGA: remove instructions to build merge_sort on Windows (#1290) * FPGA: Update printf readme and fixed some typos (#1288) * Added simulation instructions to README for 2023.1 * Corrected for running simulation since windows need multiple commmands to run * FPGA: Top level readme update (#1285) * removed dpc_common.hpp dependency (#1282) Co-authored-by: Rakshith Krishnappa <[email protected]> * FPGA: add simulation support to the private_copies samples (#1296) * Reverted PR#1265 and PR#1266 (#1298) * Update repo Readme.md (#1308) Update readme to reflect the current changes in repo behavior, which is that the master branch is stable and works with current released toolkits. * FPGA: Move all FPGA samples to IP Authoring, targeting Agilex by default (#1307) # Existing Sample Changes ## Description All of the FPGA samples are moved to the IP Authoring flow. The default target for all samples is now Agilex. For targeting a specific board, the user must run `cmake` with `-DFPGA_DEVICE=` his own BSP name. * matrix_mul_mkl: use single precision for compatibility with all devices (#1310) * updated latest GPU devices in Occupancy Calculator (#1309) * FPGA: add a warning when compiling the CRR design in the simulation flow (#1318) The simulation runtime of the CRR design is very long. This PR adds a message that the users can see when they compile for simulation warning them about this long runtime. * FPGA: Update throughput numbers for mvdr_beamforming design for 2023.1 release (#1325) * FPGA: Update QRD s10 default seed (#1324) This PR updates the PAC S10 default seed of the QRD design in order to meet the expected performance for 2023.1 * FPGA: Add `device_global` sample (#1291) * update the sample with mcg59 as a default engine (#1331) * FPGA: remove fp-relaxed from compile cli, use fp-precise for widnows emulator (#1321) * FPGA: create new invocation interfaces sample (#1303) * FPGA: New Code Sample `minimum_latency` (#1302) * FPGA: Fix typo (#1342) * FPGA: Add `fpga_template` sample (#1262) * FPGA: Bug fix to the functionality of the `dynamic_profiler` tutorial (#1340) * FPGA: Reduce the `decompress` test file sizes when running simulation to make the runtime faster (#1351) * Compilator update (#1349) * Change compiler in makefiles * Change compiler in cmake files * Updated TBB source files to use default_selector_v (#1360) Co-authored-by: gta <[email protected]> * update Makefile to compile with icpx (#1363) Co-authored-by: rupakroyintel <[email protected]> * FPGA: Typo for s10 support in `device_globals` (#1359) * FPGA: Add platform designer tutorial (#1348) * FPGA: prevent an out of bounds memory access in streaming_qrd.hpp (#1367) * FPGA: Move the simple-add and vector-add samples to the IP Authoring flow (#1369) * FPGA: Update onchip memory cache readme (#1358) Updated readme to match new template (with exceptions for FPGA), updated branding, updated some formatting, corrected some grammar. Updated content to reflect changes requested by reviewer. * FPGA: Remove Windows simulator command for memory_attributes (#1374) * Fix compilation error (#1371) * FPGA: replace Agilex™ with Agilex® (#1372) * FPGA: Fix decompress emulation flow not using the correct files(#1373) * FPGA: Fix race condition in the buffered_host_streaming sample (#1375) * Update FPGA optimize inner loop readme (#1380) Restructure to match new template. Updated formatting. Rewrote and restructured for clarity. Moved images to assets folder. Corrected some relative link issues (assuming master branch). * FPGA: incorrect path update (#1382) * Relax correctness test for Ch04 matrix multiply (#1378) Co-authored-by: gta <[email protected]> * FPGA: Reduce the design size of the memory_attributes design in simulation (#1383) * FPGA: Fix inconsistent device flags in 4 samples (#1384) Some of the samples required the device flags to be set using -DDEVICE_FLAG=-DAgilex rather than -DDEVICE_FLAG=Agilex. This change makes all the samples consistent with the second option. * FPGA Shannonization Sample readme update (#1386) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Added missing build and run instructions for Windows. Rewrote and restructured some sections for clarity. * FPGA: Update Host-Device Streaming using USM readme (#1391) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected some formatting. Rewrote and restructured some sections for clarity. * Update FPGA pipe array readme (#1385) Changed the sample name in the readme to match the name in the sample.json file. Restructured the readme to match the new template, with exceptions related to FPGA structure. Corrected formatting. Updated some branding. Rewrote and restructured some sections for clarity. * Revert "FPGA: Remove Windows simulator command for memory_attributes (#1374)" (#1389) This reverts commit 149dbb6. * FPGA: better fix for the concurrency issue in buffered_host_streaming (#1392) * FPGA: Reduce test size from 64 to 2 for memory_attributes simulator target (#1390) * FPGA: update gzip seed (#1381) * FPGA: improve build instructions in the READMEs for samples that require IS_BSP (#1388) * FPGA: make the decompress design use shared memory allocations in IPA flow (#1396) * FPGA: check USM support in fpga_template (#1397) * FPGA: Add the missing simulator selector to the CRR design. (#1398) * ApplicationDebugger: rely on ONEAPI_DEVICE_SELECTOR to select device. (#1387) Affected samples: array-transform, jacobi. Remove the custom selector.hpp files. Update README to use ONEAPI_DEVICE_SELECTOR instead of arguments. Update sample.json files. Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: improve the minimum_latency cmake device detection (#1399) * Triangular Loop readme update (#1393) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Corrected some formatting. Rewrote and restructured some sections for clarity. * Zero Copy Data Transfer readme update (#1394) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Rewrote and restructured some sections for clarity. * FPGA: Improve the `fpga_compile` tutorial (#1347) * FPGA: Add platform designer tutorial: Readme clarification (#1400) * FPGA compile update - fix compile problem with USM device check (#1402) * FPGA: compile - remove +/- in path (#1404) * Document that simulator for mvdr_beamforming can take a long time (#1405) * FPGA: Add note to large designs READMEs to warn users about large FPGA parts requirements (#1407) * changed the default sub-group size to 32 (#1406) Co-authored-by: Praveen Kundurthy <[email protected]> * FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414) * FPGA: Reduce test size for simple_host_streaming simulator target (#1415) * ApplicationDebugger: update make targets with ONEAPI_DEVICE_SELECTOR (#1416) Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: fix anr cmake file (#1420) The anr sample cmake file was not allowing to target parts that did not contain the keywords "agilex" or "a10" or "s10". This PR addresses this gap. * Added release.json for samples CI (#1418) * FPGA: add include path in compile command (#1423) * FPGA: fix the HW compile seed for the ivdep sample (#1427) This sample is notorious for getting a high percentage of timing failures during quartus compiles on the PAC boards. This PR fixes the seed so that we know it compiles cleanly on PAC boards. * updated GPU Occupancy Calculator with PVC GPU (#1425) * updated GPU Occupancy Calculator with PVC GPU * updated GPU names in Occupancy Calculator * Tools/ApplicationDebugger: update jacobi sample. (#1421) * Restructure the source code: - the common parts are moved to jacobi.cpp; - the computation parts have two flavors: - bugged.cpp contains computation with bugs; - fixed.cpp contains fixed computation; * Simplify reductions; * Update README. Signed-off-by: Saiapova, Natalia <[email protected]> * Update GPU-Opt-Guide examples to 2023.03.14 (#1432) * FPGA: Provide smaller input file size option for gzip (#1431) Provide the option to run gzip_ll with 100 B file so that the simulator flow takes < 2h to finish for Questa FSE. * updated oneapi_essentials module2 notebook and code sample (#1430) * updated oneapi_essentials module2 notebook and code sample * updated Makefile * Add all files (#1437) * Add all files (#1436) * Updated sample.json files for cuBLAS and matrix_mul_SYCLMigration (#1442) * change compiler for new oneDNN release (#1435) * adding Jupyter Notebooks for cuda to sycl migration learning path (#1439) * FPGA: Reduce array size for simulation in the loop_unroll sample (#1443) The loop unroll code sample's array size was 1024 for simulation which caused simulating with Questa FSE on Windows to be very slow (>24 hours). This changes the array size to 16 which lets the simulation to complete in ~1 hour using Questa FSE on Windows. * FPGA: fix incorrect paths in Windows CI steps (#1445) Some FPGA samples had incorrect path in their CI steps in the sample.json file. * Pred modeling updates (#1446) * Predictive Modeling Updates * fix complete --------- Co-authored-by: u51369 <[email protected]> * Rendering: path tracing with embree cpu updates (#1362) * First pass at CPU Embree 4 changes, need to change header Signed-off-by: Carroll, Michael R <[email protected]> * Added embree 4 headers and CMake flexibility Signed-off-by: Carroll, Michael R <[email protected]> * warning fixes for boolean Signed-off-by: Carroll, Michael R <[email protected]> * README, coherent ray updates for embree 4 Signed-off-by: Carroll, Michael R <[email protected]> * style formatting Signed-off-by: Carroll, Michael R <[email protected]> * README fixes and removal of stub mis code Signed-off-by: Carroll, Michael R <[email protected]> * Updating sample.json for dirs and ONSAM-1563 Signed-off-by: Carroll, Michael R <[email protected]> * sample.json for MacOS per ONSAM ticket Signed-off-by: Carroll, Michael R <[email protected]> * pathtracer lib ref update for macos validation consistency Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering: IntroToRayTracingWithEmbree embree4 update (#1354) * rkRayTracer Embree4 GPU: Updated sample.json for validation Signed-off-by: Carroll, Michael R <[email protected]> * Embree 4 compatibility updates for Ray Tracer Signed-off-by: Carroll, Michael R <[email protected]> * Ray Tracer Embree4 sample.json update Signed-off-by: Carroll, Michael R <[email protected]> * Firmer reference to rkcommon (macOS validation helper) Signed-off-by: Carroll, Michael R <[email protected]> * Cleaning up helper script/CMake syntax Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering Embree4 GSG Updates (#1353) * stage embree gsg for cpu Signed-off-by: MichaelRoyceCarroll <[email protected]> * Add gpu to Rendering 02_embree... TODO: test/json val/readme Signed-off-by: Carroll, Michael R <[email protected]> * Adding license file in all folders for 02_embree Signed-off-by: Carroll, Michael R <[email protected]> * Update Embree gsg README.md * Update embree4 readme.md * embree minimal samples updated for embree 4... prewindows testing Signed-off-by: Carroll, Michael R <[email protected]> * Checked on Windows, fixed readme... ready for PR review Signed-off-by: MichaelRoyceCarroll <[email protected]> * Embree4 gsg JSON automation updates Signed-off-by: Carroll, Michael R <[email protected]> * README updates... thx to @jkinsky feedback Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> * Fix double to float (#1447) * FPGA: Platform designer readme touchup (#1449) * Added SECURITY.md (#1450) * Removed Windows validation step from ciTests (#1451) * Rtk development branch fix for validation 20230320 (#1458) * sample.json update for macos validation workaround Signed-off-by: Carroll, Michael R <[email protected]> * samples.json workaround for validation rtk pathtracer Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * FPGA: Fix windows CI steps in platform designer (#1459) * Updated Makefile.win to resolve Windows compilation errors (#1460) * Updated makefile to remove sycl.lib (#1468) * Allow Ch18 DPC++ book code samples to compile (#1467) * Uncommented CMakeLists.txt for Ch18 DPC++ book code samples * Updated CMakeLists.txt * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json (#1470) * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json Signed-off-by: Natalia Saiapova <[email protected]> * Update sample.json --------- Signed-off-by: Natalia Saiapova <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> * FPGA: document RTL library issue with the 2023.1 release. (#1471) (#1472) * FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476) This is a port of #1474 * FPGA: reduce snappy decompression simulation duration (#1478) When using Questa FSE, the simulation time of the snappy decompression of Stratix 10 was excessively long, This PR reduces the problem size when running in simulation to speed up the execution time. This PR is a port of #1475. * FPGA: Set fp model to "precise" for ac_fixed sample (#1483) * set fp-model to precise for emu only * set fp-model to precise for all platforms --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]> * test oneapi ci cron job master -> gh-pages. Signed-off-by: michael vincerra <[email protected]> --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: michael vincerra <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]>

@jkinsky

…#1533) * 2023.1 Release PR (#1499) * FPGA: Update dsp_control README (#1269) * FPGA: Revert "FPGA: Remove db query 9 in 2023.0 (#1257)" (#1281) This reverts commit 86c4aa8 and reenables the db9 code sample in 2023.1 * FPGA: Batch PR - sim support - selectors update - readme rework (#1280) This PR: - adds simulation support to almost all of the remaining FPGA code samples - reworks all the FPGA code sample READMEs to update the software requirements - reworks the FPGA code samples READMEs from the Tutorials folder to now reference the FPGA top-level README and remove any duplicated information - changes all FPGA samples selectors to comply with the 2023.1 new selectors - edits all FPGA READMEs to specify to use the CL_CONTEXT_MPSIM_DEVICE_INTELFPGA environment variable when running the FPGA simulator flow * FPGA: Remove all references to Windows in README (#1273) * Update samples to SYCL 2023 specifications (#1286) * FPGA: fix io_streaming assets location (#1289) * FPGA: remove instructions to build merge_sort on Windows (#1290) * FPGA: Update printf readme and fixed some typos (#1288) * Added simulation instructions to README for 2023.1 * Corrected for running simulation since windows need multiple commmands to run * FPGA: Top level readme update (#1285) * removed dpc_common.hpp dependency (#1282) Co-authored-by: Rakshith Krishnappa <[email protected]> * FPGA: add simulation support to the private_copies samples (#1296) * Reverted PR#1265 and PR#1266 (#1298) * Update repo Readme.md (#1308) Update readme to reflect the current changes in repo behavior, which is that the master branch is stable and works with current released toolkits. * FPGA: Move all FPGA samples to IP Authoring, targeting Agilex by default (#1307) # Existing Sample Changes ## Description All of the FPGA samples are moved to the IP Authoring flow. The default target for all samples is now Agilex. For targeting a specific board, the user must run `cmake` with `-DFPGA_DEVICE=` his own BSP name. * matrix_mul_mkl: use single precision for compatibility with all devices (#1310) * updated latest GPU devices in Occupancy Calculator (#1309) * FPGA: add a warning when compiling the CRR design in the simulation flow (#1318) The simulation runtime of the CRR design is very long. This PR adds a message that the users can see when they compile for simulation warning them about this long runtime. * FPGA: Update throughput numbers for mvdr_beamforming design for 2023.1 release (#1325) * FPGA: Update QRD s10 default seed (#1324) This PR updates the PAC S10 default seed of the QRD design in order to meet the expected performance for 2023.1 * FPGA: Add `device_global` sample (#1291) * update the sample with mcg59 as a default engine (#1331) * FPGA: remove fp-relaxed from compile cli, use fp-precise for widnows emulator (#1321) * FPGA: create new invocation interfaces sample (#1303) * FPGA: New Code Sample `minimum_latency` (#1302) * FPGA: Fix typo (#1342) * FPGA: Add `fpga_template` sample (#1262) * FPGA: Bug fix to the functionality of the `dynamic_profiler` tutorial (#1340) * FPGA: Reduce the `decompress` test file sizes when running simulation to make the runtime faster (#1351) * Compilator update (#1349) * Change compiler in makefiles * Change compiler in cmake files * Updated TBB source files to use default_selector_v (#1360) Co-authored-by: gta <[email protected]> * update Makefile to compile with icpx (#1363) Co-authored-by: rupakroyintel <[email protected]> * FPGA: Typo for s10 support in `device_globals` (#1359) * FPGA: Add platform designer tutorial (#1348) * FPGA: prevent an out of bounds memory access in streaming_qrd.hpp (#1367) * FPGA: Move the simple-add and vector-add samples to the IP Authoring flow (#1369) * FPGA: Update onchip memory cache readme (#1358) Updated readme to match new template (with exceptions for FPGA), updated branding, updated some formatting, corrected some grammar. Updated content to reflect changes requested by reviewer. * FPGA: Remove Windows simulator command for memory_attributes (#1374) * Fix compilation error (#1371) * FPGA: replace Agilex™ with Agilex® (#1372) * FPGA: Fix decompress emulation flow not using the correct files(#1373) * FPGA: Fix race condition in the buffered_host_streaming sample (#1375) * Update FPGA optimize inner loop readme (#1380) Restructure to match new template. Updated formatting. Rewrote and restructured for clarity. Moved images to assets folder. Corrected some relative link issues (assuming master branch). * FPGA: incorrect path update (#1382) * Relax correctness test for Ch04 matrix multiply (#1378) Co-authored-by: gta <[email protected]> * FPGA: Reduce the design size of the memory_attributes design in simulation (#1383) * FPGA: Fix inconsistent device flags in 4 samples (#1384) Some of the samples required the device flags to be set using -DDEVICE_FLAG=-DAgilex rather than -DDEVICE_FLAG=Agilex. This change makes all the samples consistent with the second option. * FPGA Shannonization Sample readme update (#1386) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Added missing build and run instructions for Windows. Rewrote and restructured some sections for clarity. * FPGA: Update Host-Device Streaming using USM readme (#1391) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected some formatting. Rewrote and restructured some sections for clarity. * Update FPGA pipe array readme (#1385) Changed the sample name in the readme to match the name in the sample.json file. Restructured the readme to match the new template, with exceptions related to FPGA structure. Corrected formatting. Updated some branding. Rewrote and restructured some sections for clarity. * Revert "FPGA: Remove Windows simulator command for memory_attributes (#1374)" (#1389) This reverts commit 149dbb6. * FPGA: better fix for the concurrency issue in buffered_host_streaming (#1392) * FPGA: Reduce test size from 64 to 2 for memory_attributes simulator target (#1390) * FPGA: update gzip seed (#1381) * FPGA: improve build instructions in the READMEs for samples that require IS_BSP (#1388) * FPGA: make the decompress design use shared memory allocations in IPA flow (#1396) * FPGA: check USM support in fpga_template (#1397) * FPGA: Add the missing simulator selector to the CRR design. (#1398) * ApplicationDebugger: rely on ONEAPI_DEVICE_SELECTOR to select device. (#1387) Affected samples: array-transform, jacobi. Remove the custom selector.hpp files. Update README to use ONEAPI_DEVICE_SELECTOR instead of arguments. Update sample.json files. Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: improve the minimum_latency cmake device detection (#1399) * Triangular Loop readme update (#1393) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Corrected some formatting. Rewrote and restructured some sections for clarity. * Zero Copy Data Transfer readme update (#1394) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Rewrote and restructured some sections for clarity. * FPGA: Improve the `fpga_compile` tutorial (#1347) * FPGA: Add platform designer tutorial: Readme clarification (#1400) * FPGA compile update - fix compile problem with USM device check (#1402) * FPGA: compile - remove +/- in path (#1404) * Document that simulator for mvdr_beamforming can take a long time (#1405) * FPGA: Add note to large designs READMEs to warn users about large FPGA parts requirements (#1407) * changed the default sub-group size to 32 (#1406) Co-authored-by: Praveen Kundurthy <[email protected]> * FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414) * FPGA: Reduce test size for simple_host_streaming simulator target (#1415) * ApplicationDebugger: update make targets with ONEAPI_DEVICE_SELECTOR (#1416) Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: fix anr cmake file (#1420) The anr sample cmake file was not allowing to target parts that did not contain the keywords "agilex" or "a10" or "s10". This PR addresses this gap. * Added release.json for samples CI (#1418) * FPGA: add include path in compile command (#1423) * FPGA: fix the HW compile seed for the ivdep sample (#1427) This sample is notorious for getting a high percentage of timing failures during quartus compiles on the PAC boards. This PR fixes the seed so that we know it compiles cleanly on PAC boards. * updated GPU Occupancy Calculator with PVC GPU (#1425) * updated GPU Occupancy Calculator with PVC GPU * updated GPU names in Occupancy Calculator * Tools/ApplicationDebugger: update jacobi sample. (#1421) * Restructure the source code: - the common parts are moved to jacobi.cpp; - the computation parts have two flavors: - bugged.cpp contains computation with bugs; - fixed.cpp contains fixed computation; * Simplify reductions; * Update README. Signed-off-by: Saiapova, Natalia <[email protected]> * Update GPU-Opt-Guide examples to 2023.03.14 (#1432) * FPGA: Provide smaller input file size option for gzip (#1431) Provide the option to run gzip_ll with 100 B file so that the simulator flow takes < 2h to finish for Questa FSE. * updated oneapi_essentials module2 notebook and code sample (#1430) * updated oneapi_essentials module2 notebook and code sample * updated Makefile * Add all files (#1437) * Add all files (#1436) * Updated sample.json files for cuBLAS and matrix_mul_SYCLMigration (#1442) * change compiler for new oneDNN release (#1435) * adding Jupyter Notebooks for cuda to sycl migration learning path (#1439) * FPGA: Reduce array size for simulation in the loop_unroll sample (#1443) The loop unroll code sample's array size was 1024 for simulation which caused simulating with Questa FSE on Windows to be very slow (>24 hours). This changes the array size to 16 which lets the simulation to complete in ~1 hour using Questa FSE on Windows. * FPGA: fix incorrect paths in Windows CI steps (#1445) Some FPGA samples had incorrect path in their CI steps in the sample.json file. * Pred modeling updates (#1446) * Predictive Modeling Updates * fix complete --------- Co-authored-by: u51369 <[email protected]> * Rendering: path tracing with embree cpu updates (#1362) * First pass at CPU Embree 4 changes, need to change header Signed-off-by: Carroll, Michael R <[email protected]> * Added embree 4 headers and CMake flexibility Signed-off-by: Carroll, Michael R <[email protected]> * warning fixes for boolean Signed-off-by: Carroll, Michael R <[email protected]> * README, coherent ray updates for embree 4 Signed-off-by: Carroll, Michael R <[email protected]> * style formatting Signed-off-by: Carroll, Michael R <[email protected]> * README fixes and removal of stub mis code Signed-off-by: Carroll, Michael R <[email protected]> * Updating sample.json for dirs and ONSAM-1563 Signed-off-by: Carroll, Michael R <[email protected]> * sample.json for MacOS per ONSAM ticket Signed-off-by: Carroll, Michael R <[email protected]> * pathtracer lib ref update for macos validation consistency Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering: IntroToRayTracingWithEmbree embree4 update (#1354) * rkRayTracer Embree4 GPU: Updated sample.json for validation Signed-off-by: Carroll, Michael R <[email protected]> * Embree 4 compatibility updates for Ray Tracer Signed-off-by: Carroll, Michael R <[email protected]> * Ray Tracer Embree4 sample.json update Signed-off-by: Carroll, Michael R <[email protected]> * Firmer reference to rkcommon (macOS validation helper) Signed-off-by: Carroll, Michael R <[email protected]> * Cleaning up helper script/CMake syntax Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering Embree4 GSG Updates (#1353) * stage embree gsg for cpu Signed-off-by: MichaelRoyceCarroll <[email protected]> * Add gpu to Rendering 02_embree... TODO: test/json val/readme Signed-off-by: Carroll, Michael R <[email protected]> * Adding license file in all folders for 02_embree Signed-off-by: Carroll, Michael R <[email protected]> * Update Embree gsg README.md * Update embree4 readme.md * embree minimal samples updated for embree 4... prewindows testing Signed-off-by: Carroll, Michael R <[email protected]> * Checked on Windows, fixed readme... ready for PR review Signed-off-by: MichaelRoyceCarroll <[email protected]> * Embree4 gsg JSON automation updates Signed-off-by: Carroll, Michael R <[email protected]> * README updates... thx to @jkinsky feedback Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> * Fix double to float (#1447) * FPGA: Platform designer readme touchup (#1449) * Added SECURITY.md (#1450) * Removed Windows validation step from ciTests (#1451) * Rtk development branch fix for validation 20230320 (#1458) * sample.json update for macos validation workaround Signed-off-by: Carroll, Michael R <[email protected]> * samples.json workaround for validation rtk pathtracer Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * FPGA: Fix windows CI steps in platform designer (#1459) * Updated Makefile.win to resolve Windows compilation errors (#1460) * Updated makefile to remove sycl.lib (#1468) * Allow Ch18 DPC++ book code samples to compile (#1467) * Uncommented CMakeLists.txt for Ch18 DPC++ book code samples * Updated CMakeLists.txt * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json (#1470) * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json Signed-off-by: Natalia Saiapova <[email protected]> * Update sample.json --------- Signed-off-by: Natalia Saiapova <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> * FPGA: document RTL library issue with the 2023.1 release. (#1471) (#1472) * FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476) This is a port of #1474 * FPGA: reduce snappy decompression simulation duration (#1478) When using Questa FSE, the simulation time of the snappy decompression of Stratix 10 was excessively long, This PR reduces the problem size when running in simulation to speed up the execution time. This PR is a port of #1475. * FPGA: Set fp model to "precise" for ac_fixed sample (#1483) * set fp-model to precise for emu only * set fp-model to precise for all platforms --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]> * comment out 'trigger' lines in CI job until further testing complete. Signed-off-by: michael vincerra <[email protected]> --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: michael vincerra <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]>

@jkinsky

* 2023.1 Release PR (#1499) * FPGA: Update dsp_control README (#1269) * FPGA: Revert "FPGA: Remove db query 9 in 2023.0 (#1257)" (#1281) This reverts commit 86c4aa8 and reenables the db9 code sample in 2023.1 * FPGA: Batch PR - sim support - selectors update - readme rework (#1280) This PR: - adds simulation support to almost all of the remaining FPGA code samples - reworks all the FPGA code sample READMEs to update the software requirements - reworks the FPGA code samples READMEs from the Tutorials folder to now reference the FPGA top-level README and remove any duplicated information - changes all FPGA samples selectors to comply with the 2023.1 new selectors - edits all FPGA READMEs to specify to use the CL_CONTEXT_MPSIM_DEVICE_INTELFPGA environment variable when running the FPGA simulator flow * FPGA: Remove all references to Windows in README (#1273) * Update samples to SYCL 2023 specifications (#1286) * FPGA: fix io_streaming assets location (#1289) * FPGA: remove instructions to build merge_sort on Windows (#1290) * FPGA: Update printf readme and fixed some typos (#1288) * Added simulation instructions to README for 2023.1 * Corrected for running simulation since windows need multiple commmands to run * FPGA: Top level readme update (#1285) * removed dpc_common.hpp dependency (#1282) Co-authored-by: Rakshith Krishnappa <[email protected]> * FPGA: add simulation support to the private_copies samples (#1296) * Reverted PR#1265 and PR#1266 (#1298) * Update repo Readme.md (#1308) Update readme to reflect the current changes in repo behavior, which is that the master branch is stable and works with current released toolkits. * FPGA: Move all FPGA samples to IP Authoring, targeting Agilex by default (#1307) # Existing Sample Changes ## Description All of the FPGA samples are moved to the IP Authoring flow. The default target for all samples is now Agilex. For targeting a specific board, the user must run `cmake` with `-DFPGA_DEVICE=` his own BSP name. * matrix_mul_mkl: use single precision for compatibility with all devices (#1310) * updated latest GPU devices in Occupancy Calculator (#1309) * FPGA: add a warning when compiling the CRR design in the simulation flow (#1318) The simulation runtime of the CRR design is very long. This PR adds a message that the users can see when they compile for simulation warning them about this long runtime. * FPGA: Update throughput numbers for mvdr_beamforming design for 2023.1 release (#1325) * FPGA: Update QRD s10 default seed (#1324) This PR updates the PAC S10 default seed of the QRD design in order to meet the expected performance for 2023.1 * FPGA: Add `device_global` sample (#1291) * update the sample with mcg59 as a default engine (#1331) * FPGA: remove fp-relaxed from compile cli, use fp-precise for widnows emulator (#1321) * FPGA: create new invocation interfaces sample (#1303) * FPGA: New Code Sample `minimum_latency` (#1302) * FPGA: Fix typo (#1342) * FPGA: Add `fpga_template` sample (#1262) * FPGA: Bug fix to the functionality of the `dynamic_profiler` tutorial (#1340) * FPGA: Reduce the `decompress` test file sizes when running simulation to make the runtime faster (#1351) * Compilator update (#1349) * Change compiler in makefiles * Change compiler in cmake files * Updated TBB source files to use default_selector_v (#1360) Co-authored-by: gta <[email protected]> * update Makefile to compile with icpx (#1363) Co-authored-by: rupakroyintel <[email protected]> * FPGA: Typo for s10 support in `device_globals` (#1359) * FPGA: Add platform designer tutorial (#1348) * FPGA: prevent an out of bounds memory access in streaming_qrd.hpp (#1367) * FPGA: Move the simple-add and vector-add samples to the IP Authoring flow (#1369) * FPGA: Update onchip memory cache readme (#1358) Updated readme to match new template (with exceptions for FPGA), updated branding, updated some formatting, corrected some grammar. Updated content to reflect changes requested by reviewer. * FPGA: Remove Windows simulator command for memory_attributes (#1374) * Fix compilation error (#1371) * FPGA: replace Agilex™ with Agilex® (#1372) * FPGA: Fix decompress emulation flow not using the correct files(#1373) * FPGA: Fix race condition in the buffered_host_streaming sample (#1375) * Update FPGA optimize inner loop readme (#1380) Restructure to match new template. Updated formatting. Rewrote and restructured for clarity. Moved images to assets folder. Corrected some relative link issues (assuming master branch). * FPGA: incorrect path update (#1382) * Relax correctness test for Ch04 matrix multiply (#1378) Co-authored-by: gta <[email protected]> * FPGA: Reduce the design size of the memory_attributes design in simulation (#1383) * FPGA: Fix inconsistent device flags in 4 samples (#1384) Some of the samples required the device flags to be set using -DDEVICE_FLAG=-DAgilex rather than -DDEVICE_FLAG=Agilex. This change makes all the samples consistent with the second option. * FPGA Shannonization Sample readme update (#1386) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Added missing build and run instructions for Windows. Rewrote and restructured some sections for clarity. * FPGA: Update Host-Device Streaming using USM readme (#1391) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected some formatting. Rewrote and restructured some sections for clarity. * Update FPGA pipe array readme (#1385) Changed the sample name in the readme to match the name in the sample.json file. Restructured the readme to match the new template, with exceptions related to FPGA structure. Corrected formatting. Updated some branding. Rewrote and restructured some sections for clarity. * Revert "FPGA: Remove Windows simulator command for memory_attributes (#1374)" (#1389) This reverts commit 149dbb6. * FPGA: better fix for the concurrency issue in buffered_host_streaming (#1392) * FPGA: Reduce test size from 64 to 2 for memory_attributes simulator target (#1390) * FPGA: update gzip seed (#1381) * FPGA: improve build instructions in the READMEs for samples that require IS_BSP (#1388) * FPGA: make the decompress design use shared memory allocations in IPA flow (#1396) * FPGA: check USM support in fpga_template (#1397) * FPGA: Add the missing simulator selector to the CRR design. (#1398) * ApplicationDebugger: rely on ONEAPI_DEVICE_SELECTOR to select device. (#1387) Affected samples: array-transform, jacobi. Remove the custom selector.hpp files. Update README to use ONEAPI_DEVICE_SELECTOR instead of arguments. Update sample.json files. Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: improve the minimum_latency cmake device detection (#1399) * Triangular Loop readme update (#1393) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Corrected some formatting. Rewrote and restructured some sections for clarity. * Zero Copy Data Transfer readme update (#1394) Changed sample name in readme to match name in sample.json file. Restructured to match new template, with exceptions for FPGA structure. Moved images into “assets” subfolder. Corrected formatting. Rewrote and restructured some sections for clarity. * FPGA: Improve the `fpga_compile` tutorial (#1347) * FPGA: Add platform designer tutorial: Readme clarification (#1400) * FPGA compile update - fix compile problem with USM device check (#1402) * FPGA: compile - remove +/- in path (#1404) * Document that simulator for mvdr_beamforming can take a long time (#1405) * FPGA: Add note to large designs READMEs to warn users about large FPGA parts requirements (#1407) * changed the default sub-group size to 32 (#1406) Co-authored-by: Praveen Kundurthy <[email protected]> * FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414) * FPGA: Reduce test size for simple_host_streaming simulator target (#1415) * ApplicationDebugger: update make targets with ONEAPI_DEVICE_SELECTOR (#1416) Signed-off-by: Natalia Saiapova <[email protected]> * FPGA: fix anr cmake file (#1420) The anr sample cmake file was not allowing to target parts that did not contain the keywords "agilex" or "a10" or "s10". This PR addresses this gap. * Added release.json for samples CI (#1418) * FPGA: add include path in compile command (#1423) * FPGA: fix the HW compile seed for the ivdep sample (#1427) This sample is notorious for getting a high percentage of timing failures during quartus compiles on the PAC boards. This PR fixes the seed so that we know it compiles cleanly on PAC boards. * updated GPU Occupancy Calculator with PVC GPU (#1425) * updated GPU Occupancy Calculator with PVC GPU * updated GPU names in Occupancy Calculator * Tools/ApplicationDebugger: update jacobi sample. (#1421) * Restructure the source code: - the common parts are moved to jacobi.cpp; - the computation parts have two flavors: - bugged.cpp contains computation with bugs; - fixed.cpp contains fixed computation; * Simplify reductions; * Update README. Signed-off-by: Saiapova, Natalia <[email protected]> * Update GPU-Opt-Guide examples to 2023.03.14 (#1432) * FPGA: Provide smaller input file size option for gzip (#1431) Provide the option to run gzip_ll with 100 B file so that the simulator flow takes < 2h to finish for Questa FSE. * updated oneapi_essentials module2 notebook and code sample (#1430) * updated oneapi_essentials module2 notebook and code sample * updated Makefile * Add all files (#1437) * Add all files (#1436) * Updated sample.json files for cuBLAS and matrix_mul_SYCLMigration (#1442) * change compiler for new oneDNN release (#1435) * adding Jupyter Notebooks for cuda to sycl migration learning path (#1439) * FPGA: Reduce array size for simulation in the loop_unroll sample (#1443) The loop unroll code sample's array size was 1024 for simulation which caused simulating with Questa FSE on Windows to be very slow (>24 hours). This changes the array size to 16 which lets the simulation to complete in ~1 hour using Questa FSE on Windows. * FPGA: fix incorrect paths in Windows CI steps (#1445) Some FPGA samples had incorrect path in their CI steps in the sample.json file. * Pred modeling updates (#1446) * Predictive Modeling Updates * fix complete --------- Co-authored-by: u51369 <[email protected]> * Rendering: path tracing with embree cpu updates (#1362) * First pass at CPU Embree 4 changes, need to change header Signed-off-by: Carroll, Michael R <[email protected]> * Added embree 4 headers and CMake flexibility Signed-off-by: Carroll, Michael R <[email protected]> * warning fixes for boolean Signed-off-by: Carroll, Michael R <[email protected]> * README, coherent ray updates for embree 4 Signed-off-by: Carroll, Michael R <[email protected]> * style formatting Signed-off-by: Carroll, Michael R <[email protected]> * README fixes and removal of stub mis code Signed-off-by: Carroll, Michael R <[email protected]> * Updating sample.json for dirs and ONSAM-1563 Signed-off-by: Carroll, Michael R <[email protected]> * sample.json for MacOS per ONSAM ticket Signed-off-by: Carroll, Michael R <[email protected]> * pathtracer lib ref update for macos validation consistency Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering: IntroToRayTracingWithEmbree embree4 update (#1354) * rkRayTracer Embree4 GPU: Updated sample.json for validation Signed-off-by: Carroll, Michael R <[email protected]> * Embree 4 compatibility updates for Ray Tracer Signed-off-by: Carroll, Michael R <[email protected]> * Ray Tracer Embree4 sample.json update Signed-off-by: Carroll, Michael R <[email protected]> * Firmer reference to rkcommon (macOS validation helper) Signed-off-by: Carroll, Michael R <[email protected]> * Cleaning up helper script/CMake syntax Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * Rendering Embree4 GSG Updates (#1353) * stage embree gsg for cpu Signed-off-by: MichaelRoyceCarroll <[email protected]> * Add gpu to Rendering 02_embree... TODO: test/json val/readme Signed-off-by: Carroll, Michael R <[email protected]> * Adding license file in all folders for 02_embree Signed-off-by: Carroll, Michael R <[email protected]> * Update Embree gsg README.md * Update embree4 readme.md * embree minimal samples updated for embree 4... prewindows testing Signed-off-by: Carroll, Michael R <[email protected]> * Checked on Windows, fixed readme... ready for PR review Signed-off-by: MichaelRoyceCarroll <[email protected]> * Embree4 gsg JSON automation updates Signed-off-by: Carroll, Michael R <[email protected]> * README updates... thx to @jkinsky feedback Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> * Fix double to float (#1447) * FPGA: Platform designer readme touchup (#1449) * Added SECURITY.md (#1450) * Removed Windows validation step from ciTests (#1451) * Rtk development branch fix for validation 20230320 (#1458) * sample.json update for macos validation workaround Signed-off-by: Carroll, Michael R <[email protected]> * samples.json workaround for validation rtk pathtracer Signed-off-by: Carroll, Michael R <[email protected]> --------- Signed-off-by: Carroll, Michael R <[email protected]> * FPGA: Fix windows CI steps in platform designer (#1459) * Updated Makefile.win to resolve Windows compilation errors (#1460) * Updated makefile to remove sycl.lib (#1468) * Allow Ch18 DPC++ book code samples to compile (#1467) * Uncommented CMakeLists.txt for Ch18 DPC++ book code samples * Updated CMakeLists.txt * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json (#1470) * Tools/ApplicationDebugger/jacobi: remove Windows from sample.json Signed-off-by: Natalia Saiapova <[email protected]> * Update sample.json --------- Signed-off-by: Natalia Saiapova <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> * FPGA: document RTL library issue with the 2023.1 release. (#1471) (#1472) * FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476) This is a port of #1474 * FPGA: reduce snappy decompression simulation duration (#1478) When using Questa FSE, the simulation time of the snappy decompression of Stratix 10 was excessively long, This PR reduces the problem size when running in simulation to speed up the execution time. This PR is a port of #1475. * FPGA: Set fp model to "precise" for ac_fixed sample (#1483) * set fp-model to precise for emu only * set fp-model to precise for all platforms --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]> * Fixed merge issue in dbdata.cpp (#1501) * Add entry in third-party-programs.txt for use of Google Fonts API (#1503) - Google fonts are used in the oneAPI Samples Catalog. Signed-off-by: michael vincerra <[email protected]> * updated Jupyter notebooks for C2S based on DX testing --------- Signed-off-by: Natalia Saiapova <[email protected]> Signed-off-by: Saiapova, Natalia <[email protected]> Signed-off-by: Carroll, Michael R <[email protected]> Signed-off-by: MichaelRoyceCarroll <[email protected]> Signed-off-by: michael vincerra <[email protected]> Co-authored-by: Jimmy Wei <[email protected]> Co-authored-by: Shuo Niu <[email protected]> Co-authored-by: Justin Rosner <[email protected]> Co-authored-by: yuguen-intel <[email protected]> Co-authored-by: Peng Tu <[email protected]> Co-authored-by: Hao Xiang Yang <[email protected]> Co-authored-by: Rakshith Krishnappa <[email protected]> Co-authored-by: Artem Radzikhovskyy <[email protected]> Co-authored-by: jkinsky <[email protected]> Co-authored-by: petercad <[email protected]> Co-authored-by: Andrei Fedorov <[email protected]> Co-authored-by: Brox Chen <[email protected]> Co-authored-by: intel-jisheng1 <[email protected]> Co-authored-by: Paul White <[email protected]> Co-authored-by: alisanikiforova <[email protected]> Co-authored-by: IgorOchocki <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: Roy-Rupak <[email protected]> Co-authored-by: rupakroyintel <[email protected]> Co-authored-by: intel-liudean <[email protected]> Co-authored-by: gta <[email protected]> Co-authored-by: nsaiapova <[email protected]> Co-authored-by: Kevin Xu <[email protected]> Co-authored-by: praveenkk123 <[email protected]> Co-authored-by: Praveen Kundurthy <[email protected]> Co-authored-by: Louie Tsai <[email protected]> Co-authored-by: IlanTruanovsky <[email protected]> Co-authored-by: bjodom <[email protected]> Co-authored-by: u51369 <[email protected]> Co-authored-by: MichaelRCarroll-Intel <[email protected]> Co-authored-by: MichaelRoyceCarroll <[email protected]> Co-authored-by: wangdi4 <[email protected]> Co-authored-by: michael vincerra <[email protected]>

whitepau added 9 commits December 7, 2022 01:44

add fpga_template source code from add-empty-design branch

935ba83

add support for 2023.1 and 2023.0

6167e7b

fix for errant clang-format

9fa0534

add note about CL... environment variable

4736d41

improve verbosity of CMake file. open issue: doesn't print object file

98a0dfc

Revert "improve verbosity of CMake file. open issue: doesn't print ob…

259be82

…ject file" This reverts commit 98a0dfc.

clean up CMakeLists environment variables

539bba7

fix bug in CMakeLists (missing Xstarget)

9e78584

Merge branch 'oneapi-src:master' into add-fpga_template

1242e91

jimmytwei added the FPGA label Dec 12, 2022

jimmytwei requested a review from yuguen December 12, 2022 16:21

yuguen added 2023.1 New Sample 2023.1 labels Dec 12, 2022

yuguen requested review from pmpeter1 and tomlenth December 12, 2022 16:28

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yuguen changed the title ~~Add fpga template~~ FGPA: Add fpga_template sample Dec 15, 2022

yuguen changed the title ~~FGPA: Add fpga_template sample~~ FPGA: Add fpga_template sample Dec 15, 2022

whitepau added 3 commits December 15, 2022 08:38

update readme per Yohann's requests

fabe2ee

Merge branch 'add-fpga_template' of https://github.com/whitepau/oneAP…

3ab9516

…I-samples into add-fpga_template

add support for additional include paths

19b52dd

yuguen reviewed Dec 16, 2022

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yuguen reviewed Dec 19, 2022

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...Programming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt Outdated Show resolved Hide resolved

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yuguen changed the base branch from master to development January 6, 2023 10:06

whitepau added 4 commits January 16, 2023 05:34

Merge branch 'master' into add-fpga_template

5fcf38b

use One True CMake file

3497ef4

remove lib paths and lib because it doesn't work on windows

96ea182

minor readme tweaks

593508d

minor edits from yohann's code review

f242ce9

whitepau commented Jan 23, 2023

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Update DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_t…

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…emplate/README.md formatting Co-authored-by: yuguen-intel <[email protected]>

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tomlenth requested a review from jkinsky January 23, 2023 18:06

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jkinsky approved these changes Jan 23, 2023

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fix flag outputs for fpga target

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yuguen approved these changes Jan 24, 2023

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pmpeter1 requested changes Jan 27, 2023

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code style improvements

5bbf85d

whitepau commented Jan 30, 2023

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update readme to be compliant with IPA/Intel® Agilex® defaults

f19a571

yuguen approved these changes Feb 1, 2023

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pmpeter1 requested changes Feb 1, 2023

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simplify as per Paul Pedersen's feedback

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pmpeter1 reviewed Feb 3, 2023

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remove redundant 'public'

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whitepau requested a review from pmpeter1 February 7, 2023 14:11

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yuguen merged commit 1e2fdf0 into oneapi-src:development Feb 10, 2023

whitepau deleted the add-fpga_template branch April 20, 2023 12:18

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FPGA: Add `fpga_template` sample #1262

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FPGA: Add fpga_template sample #1262

FPGA: Add fpga_template sample #1262

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FPGA: Add `fpga_template` sample #1262

FPGA: Add `fpga_template` sample #1262

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