Fpga compile - remove +/- in path

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md

@@ -224,13 +224,13 @@ Part 4 shows the vector addition in SYCL* C++ with a 'function' coding style and
 #### On a Linux* System
 For different parts of this tutorial, navigate to the appropriate sub-folder.
 ```bash
-cd <partX-XXX>
+cd <partX_XXX>
 ```
-`<partX-XXX>` can be:
-- `part1-C++`
-- `part2-dpcpp_functor_usm`
-- `part3-dpcpp_lambda_usm`
-- `part4-dpcpp_lambda_buffers`
+`<partX_XXX>` can be:
+- `part1_cpp`
+- `part2_dpcpp_functor_usm`
+- `part3_dpcpp_lambda_usm`
+- `part4_dpcpp_lambda_buffers`
 
 Generate the `Makefile` by running `cmake`.
   ```
@@ -256,13 +256,13 @@ Generate the `Makefile` by running `cmake`.
 #### On a Windows* System
 For different parts of this tutorial, navigate to the appropriate sub-folder.
 ```cmd
-cd <partX-XXX>
+cd <partX_XXX>
 ```
-`<partX-XXX>` can be:
-- `part1-C++`
-- `part2-dpcpp_functor_usm`
-- `part3-dpcpp_lambda_usm`
-- `part4-dpcpp_lambda_buffers`
+`<partX_XXX>` can be:
+- `part1_cpp`
+- `part2_dpcpp_functor_usm`
+- `part3_dpcpp_lambda_usm`
+- `part4_dpcpp_lambda_buffers`
 
 Generate the `Makefile` by running `cmake`.
   ```

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part1_cpp/src/vector_add.cpp

@@ -0,0 +1,47 @@
+#include <iostream>
+
+void VectorAdd(const int *a_in, const int *b_in, int *c_out, int len) {
+  for (int idx = 0; idx < len; idx++) {
+    int a_val = a_in[idx];
+    int b_val = b_in[idx];
+    int sum = a_val + b_val;
+    c_out[idx] = sum;
+  }
+}
+
+constexpr int kVectSize = 256;
+
+int main() {
+  // declare arrays and fill them
+  int *vec_a = new int[kVectSize];
+  int *vec_b = new int[kVectSize];
+  int *vec_c = new int[kVectSize];
+  for (int i = 0; i < kVectSize; i++) {
+    vec_a[i] = i;
+    vec_b[i] = (kVectSize - i);
+  }
+
+  std::cout << "add two vectors of size " << kVectSize << std::endl;
+
+  VectorAdd(vec_a, vec_b, vec_c, kVectSize);
+
+  // verify that vector C is correct
+  bool passed = true;
+  for (int i = 0; i < kVectSize; i++) {
+    int expected = vec_a[i] + vec_b[i];
+    if (vec_c[i] != expected) {
+      std::cout << "idx=" << i << ": result " << vec_c[i] << ", expected ("
+                << expected << ") A=" << vec_a[i] << " + B=" << vec_b[i]
+                << std::endl;
+      passed = false;
+    }
+  }
+
+  std::cout << (passed ? "PASSED" : "FAILED") << std::endl;
+
+  delete[] vec_a;
+  delete[] vec_b;
+  delete[] vec_c;
+
+  return passed ? EXIT_SUCCESS : EXIT_FAILURE;
+}

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src/vector_add.cpp

@@ -0,0 +1,103 @@
+#include <iostream>
+
+// oneAPI headers
+#include <sycl/ext/intel/fpga_extensions.hpp>
+#include <sycl/sycl.hpp>
+
+// Forward declare the kernel name in the global scope. This is an FPGA best
+// practice that reduces name mangling in the optimization reports.
+class VectorAddID;
+
+struct VectorAdd {
+  int *const vec_a_in;
+  int *const vec_b_in;
+  int *const vec_c_out;
+  int len;
+
+  void operator()() const {
+    for (int idx = 0; idx < len; idx++) {
+      int a_val = vec_a_in[idx];
+      int b_val = vec_b_in[idx];
+      int sum = a_val + b_val;
+      vec_c_out[idx] = sum;
+    }
+  }
+};
+
+constexpr int kVectSize = 256;
+
+int main() {
+  bool passed = true;
+  try {
+    // Use compile-time macros to select either:
+    //  - the FPGA emulator device (CPU emulation of the FPGA)
+    //  - the FPGA device (a real FPGA)
+    //  - the simulator device
+#if FPGA_SIMULATOR
+    auto selector = sycl::ext::intel::fpga_simulator_selector_v;
+#elif FPGA_HARDWARE
+    auto selector = sycl::ext::intel::fpga_selector_v;
+#else  // #if FPGA_EMULATOR
+    auto selector = sycl::ext::intel::fpga_emulator_selector_v;
+#endif
+
+    // create the device queue
+    sycl::queue q(selector);
+
+    auto device = q.get_device();
+
+    std::cout << "Running on device: "
+              << device.get_info<sycl::info::device::name>().c_str()
+              << std::endl;
+
+    if (!device.has(sycl::aspect::usm_host_allocations)) {
+      std::terminate();
+    }
+
+    // declare arrays and fill them
+    // allocate in shared memory so the kernel can see them
+    int *vec_a = sycl::malloc_shared<int>(kVectSize, q);
+    int *vec_b = sycl::malloc_shared<int>(kVectSize, q);
+    int *vec_c = sycl::malloc_shared<int>(kVectSize, q);
+    for (int i = 0; i < kVectSize; i++) {
+      vec_a[i] = i;
+      vec_b[i] = (kVectSize - i);
+    }
+
+    std::cout << "add two vectors of size " << kVectSize << std::endl;
+
+    q.single_task<VectorAddID>(VectorAdd{vec_a, vec_b, vec_c, kVectSize})
+        .wait();
+
+    // verify that vec_c is correct
+    for (int i = 0; i < kVectSize; i++) {
+      int expected = vec_a[i] + vec_b[i];
+      if (vec_c[i] != expected) {
+        std::cout << "idx=" << i << ": result " << vec_c[i] << ", expected ("
+                  << expected << ") A=" << vec_a[i] << " + B=" << vec_b[i]
+                  << std::endl;
+        passed = false;
+      }
+    }
+
+    std::cout << (passed ? "PASSED" : "FAILED") << std::endl;
+
+    sycl::free(vec_a, q);
+    sycl::free(vec_b, q);
+    sycl::free(vec_c, q);
+  } catch (sycl::exception const &e) {
+    // Catches exceptions in the host code.
+    std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";
+
+    // Most likely the runtime couldn't find FPGA hardware!
+    if (e.code().value() == CL_DEVICE_NOT_FOUND) {
+      std::cerr << "If you are targeting an FPGA, please ensure that your "
+                   "system has a correctly configured FPGA board.\n";
+      std::cerr << "Run sys_check in the oneAPI root directory to verify.\n";
+      std::cerr << "If you are targeting the FPGA emulator, compile with "
+                   "-DFPGA_EMULATOR.\n";
+    }
+    std::terminate();
+  }
+  return passed ? EXIT_SUCCESS : EXIT_FAILURE;
+}