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merged 45 commits into from
Oct 14, 2022

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@min-jean-cho min-jean-cho marked this pull request as ready for review October 12, 2022 08:26
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min-jean-cho commented Oct 12, 2022

@msaroufim, PR for our second joint TorchServe IPEX blog. Could you please help review, thanks!

@svekars svekars requested a review from msaroufim October 12, 2022 15:27
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Fantastic blog (as usual) - thank you @min-jean-cho

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A few editorial suggestions. Also, need to fix these links:

/var/lib/jenkins/workspace/intermediate/torchserve_with_ipex.rst:2: WARNING: Duplicate explicit target name: "intel® vtune™ profiler".
 /var/lib/jenkins/workspace/intermediate/torchserve_with_ipex_2.rst:3: WARNING: Duplicate explicit target name: "config.properties"

Probably, just need to add double underscores in the link (my link <url>__)

Grokking PyTorch Intel CPU performance from first principles (Part 2)
=====================================================================

Authors: Min Jean Cho, Jing Xu, Mark Saroufim
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let's make this links to Github profiles.

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Thanks @svekars for the review. Have done so.


Throughout this blog, we'll use `Top-down Microarchitecture Analysis (TMA) <https://www.intel.com/content/www/us/en/develop/documentation/vtune-cookbook/top/methodologies/top-down-microarchitecture-analysis-method.html>`_ to profile and show that the Back End Bound (Memory Bound, Core Bound) is often the primary bottleneck for under-optimized or under-tuned deep learning workloads, and we'll demonstrate optimization techniques via Intel® Extension for PyTorch* for improving Back End Bound. We'll also use `Intel® VTune™ Profiler's Instrumentation and Tracing Technology (ITT) <https://github.com/pytorch/pytorch/issues/41001>`_ to profile at finer granularity.

*****************
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We typically don't add a table of contents like this because it's autogenerated on the right hand side under Shortcuts. It is difficult to keep a manual TOC like this up-to-date with any future changes in the content.

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I'm fine with either options, but I thought TOC would help when readers read the intro since this tutorial has lots of content. Let me know what you'd prefer !

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I suggest to remove it as we don't have it in any other tutorials.

- Intel® Extension for PyTorch* Optimizations
- Intel® Extension for PyTorch* with TorchServe
- Exercise

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Where is prerequisites? In the TOC above they are listed as first section.

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Do we need to have an explicit heading with "Prerequisites" ? The TOC is more of intended for a glance of content at one shot, rather than a link to the sections.

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It would be good to have a prerequisites section and list what the user need to know / have installed before they can complete this tutorial.

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OK. Let me try moving around some paragraphs, to heave content under each heading.

@svekars svekars requested a review from malfet October 12, 2022 22:24
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svekars commented Oct 12, 2022

Also, I've noticed a few images are too wide which creates formatting issues:

image1
image3
image2

min-jean-cho and others added 11 commits October 12, 2022 15:53
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
min-jean-cho and others added 14 commits October 12, 2022 16:18
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
Co-authored-by: Svetlana Karslioglu <[email protected]>
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Also, I've noticed a few images are too wide which creates formatting issues:

Thank you @svekars for checking on this. I've fixed the img sizes, could you check if they look fine now?

We typically don't add a table of contents like this because it's autogenerated on the right hand side under Shortcuts.

Could I have a look at this expanded (maybe a screenshot)? I want to see if they show up as I've intended.

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/var/lib/jenkins/workspace/intermediate/torchserve_with_ipex.rst:2: WARNING: Duplicate explicit target name: "intel® vtune™ profiler".
/var/lib/jenkins/workspace/intermediate/torchserve_with_ipex_2.rst:3: WARNING: Duplicate explicit target name: "config.properties"
Probably, just need to add double underscores in the link (my link __)

May I know the source of this warning if it's from an internal CI? I've tried fixing to my link __ where applicable, but not sure if this will resolve that warning.

@min-jean-cho min-jean-cho requested review from svekars and removed request for malfet October 14, 2022 07:01
Additionally, let's profile with PyTorch Profiler.

.. figure:: /_static/img/torchserve-ipex-images-2/13.png
:width: 150%
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can we please set this image to not more than 100% width since it causes a formatting issue? They should be clickable so the user should be able to enlarge them.

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All images are already changed to less than 100% width. The comment is on outdated file, prior to this change.

Additionally, let's profile with PyTorch Profiler.

.. figure:: /_static/img/torchserve-ipex-images-2/15.png
:width: 150%
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Can we please set the width to not more than 100%

When tuning CPU for optimal performance, it's useful to know where the bottleneck is. Most CPU cores have on-chip Performance Monitoring Units (PMUs). PMUs are dedicated pieces of logic within a CPU core that count specific hardware events as they occur on the system. Examples of these events may be Cache Misses or Branch Mispredictions. PMUs are used for Top-down Microarchitecture Analysis (TMA) to identify the bottlenecks. TMA consists of hierarchical levels as shown:

.. figure:: /_static/img/torchserve-ipex-images-2/2.png
:width: 130%
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Please set the width to 100%


Throughout this blog, we'll use `Top-down Microarchitecture Analysis (TMA) <https://www.intel.com/content/www/us/en/develop/documentation/vtune-cookbook/top/methodologies/top-down-microarchitecture-analysis-method.html>`_ to profile and show that the Back End Bound (Memory Bound, Core Bound) is often the primary bottleneck for under-optimized or under-tuned deep learning workloads, and we'll demonstrate optimization techniques via Intel® Extension for PyTorch* for improving Back End Bound. We'll also use `Intel® VTune™ Profiler's Instrumentation and Tracing Technology (ITT) <https://github.com/pytorch/pytorch/issues/41001>`_ to profile at finer granularity.

*****************
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I suggest to remove it as we don't have it in any other tutorials.


1. The feature has to be explicitly enabled by with *torch.autograd.profiler.emit_itt()*.

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Right, it looks like you have three headings on lines 66 - 71, meaning that TorchServe with Intel® Extension for PyTorch* and Leveraging Advanced Launcher Configuration: Memory Allocator are empty. Can we add a short overview paragraph under each of these headings?

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Thanks @svekars for the review, I have updated according to your comments. The updates are:

  • Fixed syntax of title and headings
  • Added content under each heading (moved around some existing paragraphs)
  • Removed TOC
  • all img sizes are less than 100%

@min-jean-cho min-jean-cho requested a review from svekars October 14, 2022 18:42
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LGTM! Thank you for addressing the comments.

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Thanks @svekars for the thorough review - grammatical errors, also I realize it's easier to read now with content under each heading. Thanks :)

Will you be merging this?

@msaroufim msaroufim merged commit be2eeaa into pytorch:master Oct 14, 2022
:card_description: A case study on the TorchServe inference framework optimized with Intel® Extension for PyTorch (Part 2).
:image: _static/img/thumbnails/cropped/generic-pytorch-logo.png
:link: intermediate/torchserve_with_ipex_2
:tags: Model-Optimization,Production
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Hi @svekars, I see this tutorial has been published to pytorch.org here. However, I don't see link to this tutorial in the left nav, could you pls. help check on this?
Screenshot (1374)

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Fix is coming: #2085

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