Merge #161

161: Add {M,P}SPLIM access routines found on ARMv8-M mainline extension r=thejpster a=aurabindo

I'd like to add better v8-M support. I'm not sure if this is PR has an optimal way of handling arch extension. As per ARMv8 Architecture reference manual, the baseline variant is not compatible with ARMv7-M. Only the main extension brings backward compatibility with v7-M.

This PR adds support for accessing MSPLIM and PSPLIM registers, and missing binaries for `thumbv8m.main-none-eabihf` architecture.

Co-authored-by: Aurabindo Jayamohanan <[email protected]>

Author: bors[bot]

asm-v8-main.s

@@ -0,0 +1,28 @@
+  .section .text.__msplim_r
+  .global __msplim_r
+  .thumb_func
+__msplim_r:
+  mrs r0, MSPLIM
+  bx lr
+
+  .section .text.__msplim_w
+  .global __msplim_w
+  .thumb_func
+__msplim_w:
+  msr MSPLIM, r0
+  bx lr
+
+  .section .text.__psplim_r
+  .global __psplim_r
+  .thumb_func
+__psplim_r:
+  mrs r0, PSPLIM
+  bx lr
+
+  .section .text.__psplim_w
+  .global __psplim_w
+  .thumb_func
+__psplim_w:
+  msr PSPLIM, r0
+  bx lr
+

assemble.sh

@@ -26,8 +26,12 @@ arm-none-eabi-as -march=armv8-m.base asm.s -o bin/$crate.o
 ar crs bin/thumbv8m.base-none-eabi.a bin/$crate.o
 
 arm-none-eabi-as -march=armv8-m.main asm.s -o bin/$crate.o
-ar crs bin/thumbv8m.main-none-eabi.a bin/$crate.o
+arm-none-eabi-as -march=armv8-m.main asm-v7.s -o bin/$crate-v7.o
+arm-none-eabi-as -march=armv8-m.main asm-v8-main.s -o bin/$crate-v8-main.o
+ar crs bin/thumbv8m.main-none-eabi.a bin/$crate.o bin/$crate-v7.o bin/$crate-v8-main.o
+ar crs bin/thumbv8m.main-none-eabihf.a bin/$crate.o bin/$crate-v7.o bin/$crate-v8-main.o
 
 rm bin/$crate.o
 rm bin/$crate-v7.o
 rm bin/$crate-cm7-r0p1.o
+rm bin/$crate-v8-main.o

bin/thumbv8m.main-none-eabi.a

@@ -26,9 +26,13 @@ fn main() {
         println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
         //println!("cargo:rustc-cfg=armv7em");
-    } else if target.starts_with("thumbv8m") {
+    } else if target.starts_with("thumbv8m.base") {
         println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv8m");
+    } else if target.starts_with("thumbv8m.main") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv8m");
+        println!("cargo:rustc-cfg=armv8m_main");
     }
 
     if target.ends_with("-eabihf") {

bin/thumbv8m.main-none-eabihf.a

@@ -43,6 +43,12 @@ pub mod primask;
 
 pub mod psp;
 
+#[cfg(armv8m_main)]
+pub mod msplim;
+
+#[cfg(armv8m_main)]
+pub mod psplim;
+
 // Accessing these registers requires inline assembly because their contents are tied to the current
 // stack frame
 #[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]

build.rs

@@ -0,0 +1,47 @@
+//! Main Stack Pointer Limit Register
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r;
+            unsafe { asm!("mrs $0,MSPLIM" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __msplim_r() -> u32;
+            }
+
+            __msplim_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr MSPLIM,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __msplim_w(_: u32);
+            }
+
+            __msplim_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}

src/register/mod.rs

@@ -0,0 +1,47 @@
+//! Process Stack Pointer Limit Register
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r;
+            unsafe { asm!("mrs $0,PSPLIM" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __psplim_r() -> u32;
+            }
+
+            __psplim_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr PSPLIM,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __psplim_w(_: u32);
+            }
+
+            __psplim_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}