Update for 2018 edition

CHANGELOG.md

@@ -302,10 +302,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 #![feature(used)]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt;
-extern crate stm32f30x;
-
 use core::cell::RefCell;
 
 use cortex_m::ctxt::Local;

Cargo.toml

@@ -12,6 +12,7 @@ name = "cortex-m"
 readme = "README.md"
 repository = "https://github.com/japaric/cortex-m"
 version = "0.6.0"
+edition = "2018"
 links = "cortex-m"  # prevent multiple versions of this crate to be linked together
 
 [dependencies]

src/interrupt.rs

@@ -61,7 +61,7 @@ pub fn free<F, R>(f: F) -> R
 where
     F: FnOnce(&CriticalSection) -> R,
 {
-    let primask = ::register::primask::read();
+    let primask = crate::register::primask::read();
 
     // disable interrupts
     disable();

src/itm.rs

@@ -6,7 +6,7 @@ use core::{fmt, mem, ptr, slice};
 
 use aligned::{Aligned, A4};
 
-use peripheral::itm::Stim;
+use crate::peripheral::itm::Stim;
 
 // NOTE assumes that `bytes` is 32-bit aligned
 unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {

src/lib.rs

@@ -47,4 +47,4 @@ pub mod itm;
 pub mod peripheral;
 pub mod register;
 
-pub use peripheral::Peripherals;
+pub use crate::peripheral::Peripherals;

src/macros.rs

@@ -33,8 +33,7 @@ macro_rules! iprintln {
 /// # Example
 ///
 /// ``` no_run
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {
 ///     // OK if `main` is executed only once
@@ -77,8 +76,7 @@ macro_rules! singleton {
 }
 
 /// ``` compile_fail
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {}
 ///
@@ -92,8 +90,7 @@ const CFAIL: () = ();
 
 /// ```
 /// #![deny(unsafe_code)]
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {}
 ///

src/peripheral/cbp.rs

@@ -4,7 +4,7 @@
 
 use volatile_register::WO;
 
-use peripheral::CBP;
+use crate::peripheral::CBP;
 
 /// Register block
 #[repr(C)]

src/peripheral/cpuid.rs

@@ -5,7 +5,7 @@ use volatile_register::RO;
 use volatile_register::RW;
 
 #[cfg(not(armv6m))]
-use peripheral::CPUID;
+use crate::peripheral::CPUID;
 
 /// Register block
 #[repr(C)]
@@ -104,7 +104,7 @@ impl CPUID {
         const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS;
 
         self.select_cache(level, ind);
-        ::asm::dsb();
+        crate::asm::dsb();
         let ccsidr = self.ccsidr.read();
         (
             (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16,

src/peripheral/dcb.rs

@@ -3,7 +3,7 @@
 use volatile_register::{RW, WO};
 
 use core::ptr;
-use peripheral::DCB;
+use crate::peripheral::DCB;
 
 const DCB_DEMCR_TRCENA: u32 = 1 << 24;
 

src/peripheral/dwt.rs

@@ -4,7 +4,7 @@
 use volatile_register::WO;
 use volatile_register::{RO, RW};
 
-use peripheral::DWT;
+use crate::peripheral::DWT;
 
 /// Register block
 #[repr(C)]

src/peripheral/mod.rs

@@ -8,8 +8,6 @@
 //! the [`Peripherals::take`](struct.Peripherals.html#method.take) method.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::Peripherals;
 //!
 //! fn main() {
@@ -22,8 +20,6 @@
 //! `Option`. Subsequent calls to the method will result in a `None` value being returned.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::Peripherals;
 //!
 //! fn main() {
@@ -36,8 +32,6 @@
 //! [`DWT::get_cycle_count`](struct.DWT.html#method.get_cycle_count) method.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::{DWT, Peripherals};
 //!
 //! fn main() {
@@ -56,8 +50,6 @@
 //! safe higher level abstractions.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::{DWT, Peripherals};
 //!
 //! fn main() {
@@ -81,7 +73,7 @@
 use core::marker::PhantomData;
 use core::ops;
 
-use interrupt;
+use crate::interrupt;
 
 #[cfg(not(armv6m))]
 pub mod cbp;

src/peripheral/nvic.rs

@@ -4,8 +4,8 @@ use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};
 
-use interrupt::Nr;
-use peripheral::NVIC;
+use crate::interrupt::Nr;
+use crate::peripheral::NVIC;
 
 /// Register block
 #[repr(C)]

src/peripheral/scb.rs

@@ -321,8 +321,8 @@ impl SCB {
         // Enable I-Cache
         unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Disables I-Cache if currently enabled
@@ -342,15 +342,15 @@ impl SCB {
         // Invalidate I-Cache
         cbp.iciallu();
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Returns whether the I-Cache is currently enabled
     #[inline]
     pub fn icache_enabled() -> bool {
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
 
         // NOTE(unsafe) atomic read with no side effects
         unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_IC_MASK == SCB_CCR_IC_MASK }
@@ -365,8 +365,8 @@ impl SCB {
         // Invalidate I-Cache
         cbp.iciallu();
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Enables D-cache if currently disabled
@@ -383,8 +383,8 @@ impl SCB {
         // Now turn on the DCache
         unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Disables D-cache if currently enabled
@@ -405,8 +405,8 @@ impl SCB {
     /// Returns whether the D-Cache is currently enabled
     #[inline]
     pub fn dcache_enabled() -> bool {
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
 
         // NOTE(unsafe) atomic read with no side effects
         unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_DC_MASK == SCB_CCR_DC_MASK }
@@ -432,8 +432,8 @@ impl SCB {
             }
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans D-cache
@@ -451,8 +451,8 @@ impl SCB {
             }
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans and invalidates D-cache
@@ -470,8 +470,8 @@ impl SCB {
             }
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Invalidates D-cache by address
@@ -491,7 +491,7 @@ impl SCB {
         // NOTE(unsafe) All CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
 
-        ::asm::dsb();
+        crate::asm::dsb();
 
         // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
         const LINESIZE: usize = 32;
@@ -504,8 +504,8 @@ impl SCB {
             addr += LINESIZE;
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans D-cache by address
@@ -525,7 +525,7 @@ impl SCB {
         // NOTE(unsafe) All CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
 
-        ::asm::dsb();
+        crate::asm::dsb();
 
         // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
         const LINESIZE: usize = 32;
@@ -538,8 +538,8 @@ impl SCB {
             addr += LINESIZE;
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans and invalidates D-cache by address
@@ -560,7 +560,7 @@ impl SCB {
         // NOTE(unsafe) All CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
 
-        ::asm::dsb();
+        crate::asm::dsb();
 
         // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
         const LINESIZE: usize = 32;
@@ -573,8 +573,8 @@ impl SCB {
             addr += LINESIZE;
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 }
 
@@ -622,7 +622,7 @@ impl SCB {
     /// Initiate a system reset request to reset the MCU
     #[deprecated(since = "0.6.1", note = "Use `SCB::sys_reset`")]
     pub fn system_reset(&mut self) -> ! {
-        ::asm::dsb();
+        crate::asm::dsb();
         unsafe {
             self.aircr.modify(
                 |r| {
@@ -632,16 +632,16 @@ impl SCB {
                 }, // set the bit
             )
         };
-        ::asm::dsb();
+        crate::asm::dsb();
         loop {
             // wait for the reset
-            ::asm::nop(); // avoid rust-lang/rust#28728
+            crate::asm::nop(); // avoid rust-lang/rust#28728
         }
     }
 
     /// Initiate a system reset request to reset the MCU
     pub fn sys_reset() -> ! {
-        ::asm::dsb();
+        crate::asm::dsb();
         unsafe {
             (*Self::ptr()).aircr.modify(
                 |r| {
@@ -651,10 +651,10 @@ impl SCB {
                 }, // set the bit
             )
         };
-        ::asm::dsb();
+        crate::asm::dsb();
         loop {
             // wait for the reset
-            ::asm::nop(); // avoid rust-lang/rust#28728
+            crate::asm::nop(); // avoid rust-lang/rust#28728
         }
     }
 }

src/peripheral/syst.rs

@@ -2,7 +2,7 @@
 
 use volatile_register::{RO, RW};
 
-use peripheral::SYST;
+use crate::peripheral::SYST;
 
 /// Register block
 #[repr(C)]