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Enable clippy in CI #174

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Oct 29, 2019
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9 changes: 9 additions & 0 deletions ci/script.sh
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,15 @@ main() {
if [ $TARGET = x86_64-unknown-linux-gnu ]; then
./check-blobs.sh
fi

if [ $TRAVIS_RUST_VERSION = nightly ]; then
# Get the latest nightly with a working clippy
rustup toolchain uninstall nightly
rustup set profile default
rustup default nightly
rustup target add $TARGET
cargo clippy --target $TARGET -- -D warnings
fi
}

main
1 change: 1 addition & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@
#![deny(missing_docs)]
#![no_std]
#![allow(clippy::identity_op)]
#![allow(clippy::missing_safety_doc)]

extern crate aligned;
extern crate bare_metal;
Expand Down
4 changes: 0 additions & 4 deletions src/macros.rs
Original file line number Diff line number Diff line change
Expand Up @@ -78,8 +78,6 @@ macro_rules! singleton {
/// ``` compile_fail
/// use cortex_m::singleton;
///
/// fn main() {}
///
/// fn foo() {
/// // check that the call to `uninitialized` requires unsafe
/// singleton!(: u8 = std::mem::uninitialized());
Expand All @@ -92,8 +90,6 @@ const CFAIL: () = ();
/// #![deny(unsafe_code)]
/// use cortex_m::singleton;
///
/// fn main() {}
///
/// fn foo() {
/// // check that calls to `singleton!` don't trip the `unsafe_code` lint
/// singleton!(: u8 = 0);
Expand Down
2 changes: 1 addition & 1 deletion src/peripheral/dwt.rs
Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,6 @@ impl DWT {
#[cfg(not(armv6m))]
pub fn unlock() {
// NOTE(unsafe) atomic write to a stateless, write-only register
unsafe { (*Self::ptr()).lar.write(0xC5ACCE55) }
unsafe { (*Self::ptr()).lar.write(0xC5AC_CE55) }
}
}
1 change: 1 addition & 0 deletions src/peripheral/mod.rs
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
#![allow(clippy::needless_doctest_main)]
//! Core peripherals
//!
//! # API
Expand Down
4 changes: 2 additions & 2 deletions src/peripheral/nvic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -164,7 +164,7 @@ impl NVIC {
{
// NOTE(unsafe) atomic read with no side effects
let ipr_n = unsafe { (*Self::ptr()).ipr[Self::ipr_index(&interrupt)].read() };
let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x000000ff;
let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x0000_00ff;
prio as u8
}
}
Expand Down Expand Up @@ -251,7 +251,7 @@ impl NVIC {
#[cfg(armv6m)]
{
self.ipr[Self::ipr_index(&interrupt)].modify(|value| {
let mask = 0x000000ff << Self::ipr_shift(&interrupt);
let mask = 0x0000_00ff << Self::ipr_shift(&interrupt);
let prio = u32::from(prio) << Self::ipr_shift(&interrupt);

(value & !mask) | prio
Expand Down
4 changes: 2 additions & 2 deletions src/peripheral/scb.rs
Original file line number Diff line number Diff line change
Expand Up @@ -781,7 +781,7 @@ impl SCB {
{
// NOTE(unsafe) atomic read with no side effects
let shpr = unsafe { (*Self::ptr()).shpr[usize::from((index - 8) / 4)].read() };
let prio = (shpr >> (8 * (index % 4))) & 0x000000ff;
let prio = (shpr >> (8 * (index % 4))) & 0x0000_00ff;
prio as u8
}
}
Expand Down Expand Up @@ -810,7 +810,7 @@ impl SCB {
{
self.shpr[usize::from((index - 8) / 4)].modify(|value| {
let shift = 8 * (index % 4);
let mask = 0x000000ff << shift;
let mask = 0x0000_00ff << shift;
let prio = u32::from(prio) << shift;

(value & !mask) | prio
Expand Down