Update to LLVM 18.1.0 rc 4 #169
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…ed type (llvm#82650) This fixes llvm#82606 by updating isSafeToLoadUnconditionally to handle fixed sized loads from a scalable accessed type. (cherry picked from commit b0edc1c)
Bring list of supported formats in docs back in sync with the code. (cherry picked from commit bf471c9)
When a section has the SHF_COMPRESSED flag, -p/-x dump the compressed content by default. In GNU readelf, if --decompress/-z is specified, -p/-x will dump the decompressed content. This patch implements the option. Close llvm#82507 (cherry picked from commit 26d71d9)
This commit adds information that only long strings are annotated, and with all allocators by default. To read why short string annotations are not turned on yet, read comments in a related PR: llvm#79536 Upstreamed in: 7661ade Upstream PR: llvm#80912 --------- Co-authored-by: Mark de Wever <[email protected]> Co-authored-by: Mark de Wever <[email protected]>
Manually cherry-pick 0bf4f82 (llvm#80952) and resolve conflicts Closes llvm#82570
Looking at the [release notes](https://prereleases.llvm.org/18.1.0/rc3/tools/clang/docs/ReleaseNotes.html) for clang 18.1.0rc, there's some broken links, and many issue numbers mis-formatted with an extra colon. Aside from being used inconsistently (with/without colon), I think it should be uncontroversial that `See (llvm#62707).` is better than `See (llvm#62707:).` CC @tstellar @AaronBallman Co-authored-by: Aaron Ballman <[email protected]>
…lvm#79221) Machines with vector support handle i128 in vector registers and therefore only have the small displacement available for memory accesses. Update isLegalAddressingMode() to reflect this. (cherry picked from commit 84dcf3d)
When an integer argument is promoted and *not* split (like i72 -> i128 on a new machine with vector support), the SlotVT should be i128, which is stored in VT - not ArgVT. Fixes llvm#81417 (cherry picked from commit 9c0e45d)
… intrinsic with a overflowing binary operator (llvm#82935) Alive2: https://alive2.llvm.org/ce/z/gyL7mn Fixes llvm#82884. (cherry picked from commit 892b4be)
…e point (llvm#81987) When there are phi nodes in the merge point of the if-region, we cannot do the merge. Alive2: https://alive2.llvm.org/ce/z/DbgEan Fixes llvm#70900. (cherry picked from commit f920b74)
openmp fails to build on musl since it lacks the defines for int32_t Co-authored-by: Daniel Martinez <[email protected]> (cherry picked from commit 45fe67d)
…nsupported MC/DC expressions (llvm#82464) Currently, upon seeing unsupported decisions (more than 6 conditions, or split nesting), the post-visitor hook dataTraverseStmtPost() returns a false. As a result, in the rest of tree even supported decisions will be skipped as well. Like in the below code: { // CompoundStmt a && b; // 1: BinaryOperator (supported) a && foo(b && c); // 2: BinaryOperator (not yet supported due to split // nesting) a && b; // 3: BinaryOperator (supported) } Decision 3 will not be processed at all. And only one "Decision" region will be emitted. Compiler explorer example: https://godbolt.org/z/Px61sesoo We hope to process such cases and emit two "Decision" regions (1 and 3) in the above example. (cherry picked from commit d4bfca3)
…e. (llvm#80642) (llvm#82743) f the signing scheme is different that maybe the functions assumes different behaviours and dangerous to inline them without analysing them. This should be a rare case.
llvm#82660) This symlink was added in 91a3846 to maintain backwards compatibility, but it needs to point to libLLVM.so.$MAJOR.$MINOR rather than libLLVM.so. This works better for distros that ship libLLVM.so and libLLVM.so.$MAJOR.$MINOR in separate packages and also prevents mistakes like libLLVM-19.so -> libLLVM.so -> libLLVM.so.18.1 Fixes llvm#82647 (cherry picked from commit 10c48a7)
* Consider that immediate escalating function can appear at global scope, fixing a crash * Lambda conversion to function pointer was sometimes not performed in an immediate function context when it should be. Fixes llvm#82258 (cherry picked from commit baf6bd3)
Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to ARMV8R, as it aligns with GCC defaults. After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed when trying to format an error message, thus update a format string in AssertSameExtensionFlags to account for bitmask being pre-formatted as std::string. The CHECK-PAUTH* lines in aarch64-target-features.c are updated to account for the fact that FEAT_PAUTH support and pac-ret can be enabled independently and all four combinations are possible. (cherry picked from commit a52eea6)
The Ampere1B is Ampere's third-generation core implementing a superscalar, out-of-order microarchitecture with nested virtualization, speculative side-channel mitigation and architectural support for defense against ROP/JOP style software attacks. Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all features of the second-generation Ampere1A, such as the Memory Tagging Extension and SM3/SM4 cryptography instructions. (cherry picked from commit fbba818)
The Ampere1B core is enabled with a new scheduling/pipeline model, as it provides significant updates over the Ampere1 core; it reduces latencies on many instructions, has some micro-ops reassigned between the XY and X units, and provides modelling for the instructions added since Ampere1 and Ampere1A. As this is the first model implementing the CSSC instructions, we update the UnsupportedFeatures on all other models (that have CompleteModel set). Testcases are added under llvm-mca: these showed the FullFP16 feature missing, so we are adding it in as part of this commit. This *adds tests and additional fixes* compared to the reverted llvm#81338. (cherry picked from commit dd1897c)
One of the whitespace fixes didn't get added to the commit introducing the Ampere1B model. Clean it up. (cherry picked from commit 3369e34)
llvm#77291) …n MIPS Modify: Add a global variable 'CurForbiddenSlotAttr' to save current instruction's forbidden slot and whether set reorder. This is the judgment condition for whether to add nop. We would add a couple of '.set noreorder' and '.set reorder' to wrap the current instruction and the next instruction. Then we can get previous instruction`s forbidden slot attribute and whether set reorder by 'CurForbiddenSlotAttr'. If previous instruction has forbidden slot and .set reorder is active and current instruction is CTI. Then emit a NOP after it. Fix llvm#61045. Because https://reviews.llvm.org/D158589 was 'Needs Review' state, not ending, so we commit pull request again. (cherry picked from commit 96abee5)
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then LLVM meets an internal error.
'r' is rejected by LLVM by: couldn't allocate input reg for constraint
'r'.
Fixes: llvm#64241, llvm#63632
---------
Co-authored-by: Fangrui Song <[email protected]>
(cherry picked from commit c88beb4)
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r=me |
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@nagisa On this repo, you have to click GitHub's button :) |
nagisa
approved these changes
Mar 1, 2024
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Oh yeah, it enables the merge button then. You'll know better which merge strategy to use, so I'll leave it up to you to click it. |
vext01
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May 24, 2024
Reject unsupported store instructions.
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This includes a fix to the libLLVM symlink needed to complete the update in rust-lang/rust#121395.
r? @cuviper or @nagisa