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SparrowLiiAmanieu
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Correct the instruction name and add floating point instructions
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3 files changed

+175
-87
lines changed

3 files changed

+175
-87
lines changed

crates/core_arch/src/aarch64/neon/generated.rs

+140-54
Original file line numberDiff line numberDiff line change
@@ -73,148 +73,202 @@ pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
7373
simd_eq(a, b)
7474
}
7575

76-
/// Signed Compare bitwise equal to zero
76+
/// Signed compare bitwise equal to zero
7777
#[inline]
7878
#[target_feature(enable = "neon")]
79-
#[cfg_attr(test, assert_instr(vceqz))]
79+
#[cfg_attr(test, assert_instr(cmeq))]
8080
pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t {
81-
simd_eq(a, transmute(i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)))
81+
let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
82+
simd_eq(a, transmute(b))
8283
}
8384

84-
/// Signed Compare bitwise equal to zero
85+
/// Signed compare bitwise equal to zero
8586
#[inline]
8687
#[target_feature(enable = "neon")]
87-
#[cfg_attr(test, assert_instr(vceqz))]
88+
#[cfg_attr(test, assert_instr(cmeq))]
8889
pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t {
89-
simd_eq(a, transmute(i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)))
90+
let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
91+
simd_eq(a, transmute(b))
9092
}
9193

92-
/// Signed Compare bitwise equal to zero
94+
/// Signed compare bitwise equal to zero
9395
#[inline]
9496
#[target_feature(enable = "neon")]
95-
#[cfg_attr(test, assert_instr(vceqz))]
97+
#[cfg_attr(test, assert_instr(cmeq))]
9698
pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t {
97-
simd_eq(a, transmute(i16x4::new(0, 0, 0, 0)))
99+
let b: i16x4 = i16x4::new(0, 0, 0, 0);
100+
simd_eq(a, transmute(b))
98101
}
99102

100-
/// Signed Compare bitwise equal to zero
103+
/// Signed compare bitwise equal to zero
101104
#[inline]
102105
#[target_feature(enable = "neon")]
103-
#[cfg_attr(test, assert_instr(vceqz))]
106+
#[cfg_attr(test, assert_instr(cmeq))]
104107
pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t {
105-
simd_eq(a, transmute(i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)))
108+
let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
109+
simd_eq(a, transmute(b))
106110
}
107111

108-
/// Signed Compare bitwise equal to zero
112+
/// Signed compare bitwise equal to zero
109113
#[inline]
110114
#[target_feature(enable = "neon")]
111-
#[cfg_attr(test, assert_instr(vceqz))]
115+
#[cfg_attr(test, assert_instr(cmeq))]
112116
pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t {
113-
simd_eq(a, transmute(i32x2::new(0, 0)))
117+
let b: i32x2 = i32x2::new(0, 0);
118+
simd_eq(a, transmute(b))
114119
}
115120

116-
/// Signed Compare bitwise equal to zero
121+
/// Signed compare bitwise equal to zero
117122
#[inline]
118123
#[target_feature(enable = "neon")]
119-
#[cfg_attr(test, assert_instr(vceqz))]
124+
#[cfg_attr(test, assert_instr(cmeq))]
120125
pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t {
121-
simd_eq(a, transmute(i32x4::new(0, 0, 0, 0)))
126+
let b: i32x4 = i32x4::new(0, 0, 0, 0);
127+
simd_eq(a, transmute(b))
122128
}
123129

124-
/// Signed Compare bitwise equal to zero
130+
/// Signed compare bitwise equal to zero
125131
#[inline]
126132
#[target_feature(enable = "neon")]
127-
#[cfg_attr(test, assert_instr(vceqz))]
133+
#[cfg_attr(test, assert_instr(cmeq))]
128134
pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t {
129-
simd_eq(a, transmute(i64x1::new(0)))
135+
let b: i64x1 = i64x1::new(0);
136+
simd_eq(a, transmute(b))
130137
}
131138

132-
/// Signed Compare bitwise equal to zero
139+
/// Signed compare bitwise equal to zero
133140
#[inline]
134141
#[target_feature(enable = "neon")]
135-
#[cfg_attr(test, assert_instr(vceqz))]
142+
#[cfg_attr(test, assert_instr(cmeq))]
136143
pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t {
137-
simd_eq(a, transmute(i64x2::new(0, 0)))
144+
let b: i64x2 = i64x2::new(0, 0);
145+
simd_eq(a, transmute(b))
138146
}
139147

140-
/// Signed Compare bitwise equal to zero
148+
/// Signed compare bitwise equal to zero
141149
#[inline]
142150
#[target_feature(enable = "neon")]
143-
#[cfg_attr(test, assert_instr(vceqz))]
151+
#[cfg_attr(test, assert_instr(cmeq))]
144152
pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t {
145-
simd_eq(a, transmute(i64x1::new(0)))
153+
let b: i64x1 = i64x1::new(0);
154+
simd_eq(a, transmute(b))
146155
}
147156

148-
/// Signed Compare bitwise equal to zero
157+
/// Signed compare bitwise equal to zero
149158
#[inline]
150159
#[target_feature(enable = "neon")]
151-
#[cfg_attr(test, assert_instr(vceqz))]
160+
#[cfg_attr(test, assert_instr(cmeq))]
152161
pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t {
153-
simd_eq(a, transmute(i64x2::new(0, 0)))
162+
let b: i64x2 = i64x2::new(0, 0);
163+
simd_eq(a, transmute(b))
154164
}
155165

156-
/// Unsigned Compare bitwise equal to zero
166+
/// Unsigned compare bitwise equal to zero
157167
#[inline]
158168
#[target_feature(enable = "neon")]
159-
#[cfg_attr(test, assert_instr(vceqz))]
169+
#[cfg_attr(test, assert_instr(cmeq))]
160170
pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t {
161-
simd_eq(a, transmute(u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)))
171+
let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
172+
simd_eq(a, transmute(b))
162173
}
163174

164-
/// Unsigned Compare bitwise equal to zero
175+
/// Unsigned compare bitwise equal to zero
165176
#[inline]
166177
#[target_feature(enable = "neon")]
167-
#[cfg_attr(test, assert_instr(vceqz))]
178+
#[cfg_attr(test, assert_instr(cmeq))]
168179
pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t {
169-
simd_eq(a, transmute(u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)))
180+
let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
181+
simd_eq(a, transmute(b))
170182
}
171183

172-
/// Unsigned Compare bitwise equal to zero
184+
/// Unsigned compare bitwise equal to zero
173185
#[inline]
174186
#[target_feature(enable = "neon")]
175-
#[cfg_attr(test, assert_instr(vceqz))]
187+
#[cfg_attr(test, assert_instr(cmeq))]
176188
pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t {
177-
simd_eq(a, transmute(u16x4::new(0, 0, 0, 0)))
189+
let b: u16x4 = u16x4::new(0, 0, 0, 0);
190+
simd_eq(a, transmute(b))
178191
}
179192

180-
/// Unsigned Compare bitwise equal to zero
193+
/// Unsigned compare bitwise equal to zero
181194
#[inline]
182195
#[target_feature(enable = "neon")]
183-
#[cfg_attr(test, assert_instr(vceqz))]
196+
#[cfg_attr(test, assert_instr(cmeq))]
184197
pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t {
185-
simd_eq(a, transmute(u16x8::new(0, 0, 0, 0, 0, 0, 0, 0)))
198+
let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
199+
simd_eq(a, transmute(b))
186200
}
187201

188-
/// Unsigned Compare bitwise equal to zero
202+
/// Unsigned compare bitwise equal to zero
189203
#[inline]
190204
#[target_feature(enable = "neon")]
191-
#[cfg_attr(test, assert_instr(vceqz))]
205+
#[cfg_attr(test, assert_instr(cmeq))]
192206
pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t {
193-
simd_eq(a, transmute(u32x2::new(0, 0)))
207+
let b: u32x2 = u32x2::new(0, 0);
208+
simd_eq(a, transmute(b))
194209
}
195210

196-
/// Unsigned Compare bitwise equal to zero
211+
/// Unsigned compare bitwise equal to zero
197212
#[inline]
198213
#[target_feature(enable = "neon")]
199-
#[cfg_attr(test, assert_instr(vceqz))]
214+
#[cfg_attr(test, assert_instr(cmeq))]
200215
pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t {
201-
simd_eq(a, transmute(u32x4::new(0, 0, 0, 0)))
216+
let b: u32x4 = u32x4::new(0, 0, 0, 0);
217+
simd_eq(a, transmute(b))
202218
}
203219

204-
/// Unsigned Compare bitwise equal to zero
220+
/// Unsigned compare bitwise equal to zero
205221
#[inline]
206222
#[target_feature(enable = "neon")]
207-
#[cfg_attr(test, assert_instr(vceqz))]
223+
#[cfg_attr(test, assert_instr(cmeq))]
208224
pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t {
209-
simd_eq(a, transmute(u64x1::new(0)))
225+
let b: u64x1 = u64x1::new(0);
226+
simd_eq(a, transmute(b))
210227
}
211228

212-
/// Unsigned Compare bitwise equal to zero
229+
/// Unsigned compare bitwise equal to zero
213230
#[inline]
214231
#[target_feature(enable = "neon")]
215-
#[cfg_attr(test, assert_instr(vceqz))]
232+
#[cfg_attr(test, assert_instr(cmeq))]
216233
pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t {
217-
simd_eq(a, transmute(u64x2::new(0, 0)))
234+
let b: u64x2 = u64x2::new(0, 0);
235+
simd_eq(a, transmute(b))
236+
}
237+
238+
/// Floating-point compare bitwise equal to zero
239+
#[inline]
240+
#[target_feature(enable = "neon")]
241+
#[cfg_attr(test, assert_instr(fcmeq))]
242+
pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t {
243+
let b: f32x2 = f32x2::new(0.0, 0.0);
244+
simd_eq(a, transmute(b))
245+
}
246+
247+
/// Floating-point compare bitwise equal to zero
248+
#[inline]
249+
#[target_feature(enable = "neon")]
250+
#[cfg_attr(test, assert_instr(fcmeq))]
251+
pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t {
252+
let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0);
253+
simd_eq(a, transmute(b))
254+
}
255+
256+
/// Floating-point compare bitwise equal to zero
257+
#[inline]
258+
#[target_feature(enable = "neon")]
259+
#[cfg_attr(test, assert_instr(fcmeq))]
260+
pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t {
261+
let b: f64 = 0.0;
262+
simd_eq(a, transmute(b))
263+
}
264+
265+
/// Floating-point compare bitwise equal to zero
266+
#[inline]
267+
#[target_feature(enable = "neon")]
268+
#[cfg_attr(test, assert_instr(fcmeq))]
269+
pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t {
270+
let b: f64x2 = f64x2::new(0.0, 0.0);
271+
simd_eq(a, transmute(b))
218272
}
219273

220274
/// Compare signed greater than
@@ -752,6 +806,38 @@ mod test {
752806
assert_eq!(r, e);
753807
}
754808

809+
#[simd_test(enable = "neon")]
810+
unsafe fn test_vceqz_f32() {
811+
let a: f32x2 = f32x2::new(0.0, 1.2);
812+
let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0);
813+
let r: u32x2 = transmute(vceqz_f32(transmute(a)));
814+
assert_eq!(r, e);
815+
}
816+
817+
#[simd_test(enable = "neon")]
818+
unsafe fn test_vceqzq_f32() {
819+
let a: f32x4 = f32x4::new(0.0, 1.2, 3.4, 5.6);
820+
let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0);
821+
let r: u32x4 = transmute(vceqzq_f32(transmute(a)));
822+
assert_eq!(r, e);
823+
}
824+
825+
#[simd_test(enable = "neon")]
826+
unsafe fn test_vceqz_f64() {
827+
let a: f64 = 0.0;
828+
let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
829+
let r: u64x1 = transmute(vceqz_f64(transmute(a)));
830+
assert_eq!(r, e);
831+
}
832+
833+
#[simd_test(enable = "neon")]
834+
unsafe fn test_vceqzq_f64() {
835+
let a: f64x2 = f64x2::new(0.0, 1.2);
836+
let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0);
837+
let r: u64x2 = transmute(vceqzq_f64(transmute(a)));
838+
assert_eq!(r, e);
839+
}
840+
755841
#[simd_test(enable = "neon")]
756842
unsafe fn test_vcgt_s64() {
757843
let a: i64x1 = i64x1::new(1);

crates/stdarch-gen/neon.spec

+16-6
Original file line numberDiff line numberDiff line change
@@ -136,26 +136,36 @@ arm = vceq.
136136
// we are missing float16x4_t:uint16x4_t, float16x8_t:uint16x8_t
137137
generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t
138138

139-
/// Signed Compare bitwise equal to zero
139+
/// Signed compare bitwise equal to zero
140140
name = vceqz
141141
fn = simd_eq
142142
a = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX
143-
fixed = 0
143+
fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
144144
validate FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
145145

146-
aarch64 = vceqz
146+
aarch64 = cmeq
147147
generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t, poly64x1_t:uint64x1_t, poly64x2_t:uint64x2_t
148148

149-
/// Unsigned Compare bitwise equal to zero
149+
/// Unsigned compare bitwise equal to zero
150150
name = vceqz
151151
fn = simd_eq
152152
a = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX
153-
fixed = 0
153+
fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
154154
validate TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
155155

156-
aarch64 = vceqz
156+
aarch64 = cmeq
157157
generate uint*_t, uint64x*_t
158158

159+
/// Floating-point compare bitwise equal to zero
160+
name = vceqz
161+
fn = simd_eq
162+
a = 0.0, 1.2, 3.4, 5.6
163+
fixed = 0.0, 0.0, 0.0, 0.0
164+
validate TRUE, FALSE, FALSE, FALSE
165+
166+
aarch64 = fcmeq
167+
generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t
168+
159169
////////////////////
160170
// greater then
161171
////////////////////

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