[DRAFT] intrinsics for all architectures appear in rustdoc

crates/core_arch/src/aarch64/neon/mod.rs

@@ -2812,7 +2812,7 @@ pub unsafe fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x
 #[cfg(test)]
 mod tests {
     use crate::core_arch::aarch64::test_support::*;
-    use crate::core_arch::arm::test_support::*;
+    use crate::core_arch::acle::test_support::*;
     use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*};
     use std::mem::transmute;
     use stdarch_test::simd_test;
@@ -4261,13 +4261,13 @@ mod tests {
 
 #[cfg(test)]
 #[cfg(target_endian = "little")]
-#[path = "../../arm/neon/table_lookup_tests.rs"]
+#[path = "../../acle/neon/table_lookup_tests.rs"]
 mod table_lookup_tests;
 
 #[cfg(test)]
-#[path = "../../arm/neon/shift_and_insert_tests.rs"]
+#[path = "../../acle/neon/shift_and_insert_tests.rs"]
 mod shift_and_insert_tests;
 
 #[cfg(test)]
-#[path = "../../arm/neon/load_tests.rs"]
+#[path = "../../acle/neon/load_tests.rs"]
 mod load_tests;

crates/core_arch/src/arm/crypto.rs → crates/core_arch/src/acle/crypto.rs

@@ -1,4 +1,4 @@
-use crate::core_arch::arm::{uint32x4_t, uint8x16_t};
+use crate::core_arch::acle::{uint32x4_t, uint8x16_t};
 
 #[allow(improper_ctypes)]
 extern "C" {
@@ -191,6 +191,7 @@ pub unsafe fn vsha256su1q_u32(
 
 #[cfg(test)]
 mod tests {
+    use super::*;
     use crate::core_arch::{arm::*, simd::*};
     use std::mem;
     use stdarch_test::simd_test;

crates/core_arch/src/acle/hints.rs

@@ -9,7 +9,7 @@
 /// low-power state until one of a number of asynchronous events occurs.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __wfi() {
     hint(HINT_WFI);
@@ -22,7 +22,7 @@ pub unsafe fn __wfi() {
 /// another processor.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __wfe() {
     hint(HINT_WFE);
@@ -34,7 +34,7 @@ pub unsafe fn __wfe() {
 /// system. It is a NOP on a uniprocessor system.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M, 7-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __sev() {
     hint(HINT_SEV);
@@ -49,6 +49,7 @@ pub unsafe fn __sev() {
 #[cfg(any(
     target_feature = "v8", // 32-bit ARMv8
     target_arch = "aarch64", // AArch64
+    doc,
 ))]
 #[inline(always)]
 pub unsafe fn __sevl() {
@@ -62,7 +63,7 @@ pub unsafe fn __sevl() {
 /// improve overall system performance.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __yield() {
     hint(HINT_YIELD);

crates/core_arch/src/acle/mod.rs

@@ -47,6 +47,9 @@
 //!
 //! - [ACLE Q2 2018](https://developer.arm.com/docs/101028/latest)
 
+// Only for 'neon' submodule
+#![allow(non_camel_case_types)]
+
 // 8, 7 and 6-M are supported via dedicated instructions like DMB. All other arches are supported
 // via CP15 instructions. See Section 10.1 of ACLE
 mod barrier;
@@ -65,59 +68,24 @@ mod ex;
 
 pub use self::ex::*;
 
-// Supported arches: 5TE, 7E-M. See Section 10.1 of ACLE (e.g. QADD)
-// We also include the A profile even though DSP is deprecated on that profile as of ACLE 2.0 (see
-// section 5.4.7)
-// Here we workaround the difference between LLVM's +dsp and ACLE's __ARM_FEATURE_DSP by gating on
-// '+v5te' rather than on '+dsp'
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        // >= v5TE but excludes v7-M
-        all(target_feature = "v5te", not(target_feature = "mclass")),
-        // v7E-M
-        all(target_feature = "mclass", target_feature = "dsp"),
-    )
-))]
-mod dsp;
-
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        all(target_feature = "v5te", not(target_feature = "mclass")),
-        all(target_feature = "mclass", target_feature = "dsp"),
-    )
-))]
-pub use self::dsp::*;
-
-// Supported arches: 6, 7-M. See Section 10.1 of ACLE (e.g. SSAT)
-#[cfg(all(not(target_arch = "aarch64"), target_feature = "v6",))]
-mod sat;
-
-#[cfg(all(not(target_arch = "aarch64"), target_feature = "v6",))]
-pub use self::sat::*;
-
-// Deprecated in ACLE 2.0 for the A profile but fully supported on the M and R profiles, says
-// Section 5.4.9 of ACLE. We'll expose these for the A profile even if deprecated
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        // v7-A, v7-R
-        all(target_feature = "v6", not(target_feature = "mclass")),
-        // v7E-M
-        all(target_feature = "mclass", target_feature = "dsp")
-    )
-))]
-mod simd32;
-
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        all(target_feature = "v6", not(target_feature = "mclass")),
-        all(target_feature = "mclass", target_feature = "dsp")
-    )
-))]
-pub use self::simd32::*;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+mod crc;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub use crc::*;
+
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+mod crypto;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub use self::crypto::*;
+
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub(crate) mod neon;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub use self::neon::*;
+
+#[cfg(test)]
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub(crate) mod test_support;
 
 mod sealed {
     pub trait Dmb {