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The following comment appears in the implementation of mem::swap
:
// NOTE(eddyb) SPIR-V's Logical addressing model doesn't allow for arbitrary
// reinterpretation of values as (chunkable) byte arrays, and the loop in the
// block optimization in `swap_slice` is hard to rewrite back
// into the (unoptimized) direct swapping implementation, so we disable it.
// FIXME(eddyb) the block optimization also prevents MIR optimizations from
// understanding `mem::replace`, `Option::take`, etc. - a better overall
// solution might be to make `ptr::swap_nonoverlapping` into an intrinsic, which
// a backend can choose to implement using the block optimization, or not.
This suggests that some of the guarantees provided by the reference/stdlib docs are not valid on the spirv
target architecture.
This raises a question: What guarantees are provided about which architectures the reference/stdlib docs are valid for? Is there a list, or is support guaranteed for targets in a particular tier, etc?
The context is that, for zerocopy, we'd like to be able to reason about this list of architectures so that we can guarantee that our code is sound as long as it compiles (google/zerocopy#383).
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