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Merge pull request #1251 from fpistm/UpdateL0
Update STM32L0 HAL and CMSIS drivers
2 parents 9b8a633 + b7c1346 commit 1d6d327

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163 files changed

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lines changed

‎cores/arduino/stm32/stm32_def_build.h

-2
Original file line numberDiff line numberDiff line change
@@ -266,8 +266,6 @@
266266
#define CMSIS_STARTUP_FILE "startup_stm32l052xx.s"
267267
#elif defined(STM32L053xx)
268268
#define CMSIS_STARTUP_FILE "startup_stm32l053xx.s"
269-
#elif defined(STM32L061xx)
270-
#define CMSIS_STARTUP_FILE "startup_stm32l061xx.s"
271269
#elif defined(STM32L062xx)
272270
#define CMSIS_STARTUP_FILE "startup_stm32l062xx.s"
273271
#elif defined(STM32L063xx)

‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c

+3
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,9 @@
2525
#ifdef STM32H7xx
2626
#include "stm32h7xx_hal_exti.c"
2727
#endif
28+
#ifdef STM32L0xx
29+
#include "stm32l0xx_hal_exti.c"
30+
#endif
2831
#ifdef STM32L1xx
2932
#include "stm32l1xx_hal_exti.c"
3033
#endif

‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c

+3
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
#ifdef STM32L0xx
2+
#include "stm32l0xx_hal_smbus_ex.c"
3+
#endif

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h

+5-11
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2018 STMicroelectronics.
17+
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
1818
* All rights reserved.</center></h2>
1919
*
2020
* This software component is licensed by ST under BSD 3-Clause license,
@@ -2972,7 +2972,10 @@ typedef struct
29722972
/* Reset and Clock Control */
29732973
/* */
29742974
/******************************************************************************/
2975-
2975+
/*
2976+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
2977+
*/
2978+
/* Note: No specific macro feature on this device */
29762979

29772980
/******************** Bit definition for RCC_CR register ********************/
29782981
#define RCC_CR_HSION_Pos (0U)
@@ -4644,13 +4647,7 @@ typedef struct
46444647
/*
46454648
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
46464649
*/
4647-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4648-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4649-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4650-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4651-
#else
46524650
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4653-
#endif
46544651

46554652
/******************* Bit definition for TIM_CR1 register ********************/
46564653
#define TIM_CR1_CEN_Pos (0U)
@@ -5703,9 +5700,6 @@ typedef struct
57035700
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57045701
((INSTANCE) == TIM21))
57055702

5706-
/****************** TIM Instances : supporting synchronization ****************/
5707-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5708-
57095703
/******************* TIM Instances : output(s) OCXEC register *****************/
57105704
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
57115705

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h

+4-11
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2018 STMicroelectronics.
17+
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
1818
* All rights reserved.</center></h2>
1919
*
2020
* This software component is licensed by ST under BSD 3-Clause license,
@@ -2981,7 +2981,9 @@ typedef struct
29812981
/* Reset and Clock Control */
29822982
/* */
29832983
/******************************************************************************/
2984-
2984+
/*
2985+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
2986+
*/
29852987
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
29862988

29872989
/******************** Bit definition for RCC_CR register ********************/
@@ -4697,13 +4699,7 @@ typedef struct
46974699
/*
46984700
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
46994701
*/
4700-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4701-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4702-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4703-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4704-
#else
47054702
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4706-
#endif
47074703

47084704
/******************* Bit definition for TIM_CR1 register ********************/
47094705
#define TIM_CR1_CEN_Pos (0U)
@@ -5760,9 +5756,6 @@ typedef struct
57605756
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57615757
((INSTANCE) == TIM21))
57625758

5763-
/****************** TIM Instances : supporting synchronization ****************/
5764-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5765-
57665759
/******************* TIM Instances : output(s) OCXEC register *****************/
57675760
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
57685761

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h

+4-11
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2018 STMicroelectronics.
17+
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
1818
* All rights reserved.</center></h2>
1919
*
2020
* This software component is licensed by ST under BSD 3-Clause license,
@@ -2980,7 +2980,9 @@ typedef struct
29802980
/* Reset and Clock Control */
29812981
/* */
29822982
/******************************************************************************/
2983-
2983+
/*
2984+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
2985+
*/
29842986
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
29852987

29862988
/******************** Bit definition for RCC_CR register ********************/
@@ -4690,13 +4692,7 @@ typedef struct
46904692
/*
46914693
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
46924694
*/
4693-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4694-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4695-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4696-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4697-
#else
46984695
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4699-
#endif
47004696

47014697
/******************* Bit definition for TIM_CR1 register ********************/
47024698
#define TIM_CR1_CEN_Pos (0U)
@@ -5755,9 +5751,6 @@ typedef struct
57555751
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57565752
((INSTANCE) == TIM21))
57575753

5758-
/****************** TIM Instances : supporting synchronization ****************/
5759-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5760-
57615754
/******************* TIM Instances : output(s) OCXEC register *****************/
57625755
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
57635756

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h

+4-11
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2018 STMicroelectronics.
17+
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
1818
* All rights reserved.</center></h2>
1919
*
2020
* This software component is licensed by ST under BSD 3-Clause license,
@@ -2988,7 +2988,9 @@ typedef struct
29882988
/* Reset and Clock Control */
29892989
/* */
29902990
/******************************************************************************/
2991-
2991+
/*
2992+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
2993+
*/
29922994
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
29932995

29942996
/******************** Bit definition for RCC_CR register ********************/
@@ -4738,13 +4740,7 @@ typedef struct
47384740
/*
47394741
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
47404742
*/
4741-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4742-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4743-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4744-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4745-
#else
47464743
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4747-
#endif
47484744

47494745
/******************* Bit definition for TIM_CR1 register ********************/
47504746
#define TIM_CR1_CEN_Pos (0U)
@@ -5831,9 +5827,6 @@ typedef struct
58315827
((INSTANCE) == TIM21) || \
58325828
((INSTANCE) == TIM22))
58335829

5834-
/****************** TIM Instances : supporting synchronization ****************/
5835-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5836-
58375830
/******************* TIM Instances : output(s) OCXEC register *****************/
58385831
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
58395832

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h

+4-10
Original file line numberDiff line numberDiff line change
@@ -3081,7 +3081,10 @@ typedef struct
30813081
/* Reset and Clock Control */
30823082
/* */
30833083
/******************************************************************************/
3084-
3084+
/*
3085+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
3086+
*/
3087+
/* Note: No specific macro feature on this device */
30853088

30863089
/******************** Bit definition for RCC_CR register ********************/
30873090
#define RCC_CR_HSION_Pos (0U)
@@ -4771,13 +4774,7 @@ typedef struct
47714774
/*
47724775
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
47734776
*/
4774-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4775-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4776-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4777-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4778-
#else
47794777
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4780-
#endif
47814778

47824779
/******************* Bit definition for TIM_CR1 register ********************/
47834780
#define TIM_CR1_CEN_Pos (0U)
@@ -5845,9 +5842,6 @@ typedef struct
58455842
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
58465843
((INSTANCE) == TIM21))
58475844

5848-
/****************** TIM Instances : supporting synchronization ****************/
5849-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5850-
58515845
/******************* TIM Instances : output(s) OCXEC register *****************/
58525846
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
58535847

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h

+4-10
Original file line numberDiff line numberDiff line change
@@ -3209,7 +3209,10 @@ typedef struct
32093209
/* Reset and Clock Control */
32103210
/* */
32113211
/******************************************************************************/
3212-
3212+
/*
3213+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
3214+
*/
3215+
/* Note: No specific macro feature on this device */
32133216

32143217
/******************** Bit definition for RCC_CR register ********************/
32153218
#define RCC_CR_HSION_Pos (0U)
@@ -4908,13 +4911,7 @@ typedef struct
49084911
/*
49094912
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
49104913
*/
4911-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4912-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4913-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4914-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4915-
#else
49164914
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4917-
#endif
49184915

49194916
/******************* Bit definition for TIM_CR1 register ********************/
49204917
#define TIM_CR1_CEN_Pos (0U)
@@ -5985,9 +5982,6 @@ typedef struct
59855982
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
59865983
((INSTANCE) == TIM21))
59875984

5988-
/****************** TIM Instances : supporting synchronization ****************/
5989-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5990-
59915985
/******************* TIM Instances : output(s) OCXEC register *****************/
59925986
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
59935987

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h

+5-10
Original file line numberDiff line numberDiff line change
@@ -3147,8 +3147,12 @@ typedef struct
31473147
/* Reset and Clock Control */
31483148
/* */
31493149
/******************************************************************************/
3150-
3150+
/*
3151+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
3152+
*/
31513153
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
3154+
#define RCC_MCO3_SUPPORT /*!<Support MCO3 */
3155+
#define RCC_MCO3_AF2_SUPPORT /*!<Support MCO3 on Alternate Function AF0 */
31523156

31533157
/******************** Bit definition for RCC_CR register ********************/
31543158
#define RCC_CR_HSION_Pos (0U)
@@ -4893,13 +4897,7 @@ typedef struct
48934897
/*
48944898
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
48954899
*/
4896-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
4897-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
4898-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4899-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
4900-
#else
49014900
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
4902-
#endif
49034901

49044902
/******************* Bit definition for TIM_CR1 register ********************/
49054903
#define TIM_CR1_CEN_Pos (0U)
@@ -5989,9 +5987,6 @@ typedef struct
59895987
((INSTANCE) == TIM21) || \
59905988
((INSTANCE) == TIM22))
59915989

5992-
/****************** TIM Instances : supporting synchronization ****************/
5993-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5994-
59955990
/******************* TIM Instances : output(s) OCXEC register *****************/
59965991
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
59975992

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h

+5-10
Original file line numberDiff line numberDiff line change
@@ -3275,8 +3275,12 @@ typedef struct
32753275
/* Reset and Clock Control */
32763276
/* */
32773277
/******************************************************************************/
3278-
3278+
/*
3279+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
3280+
*/
32793281
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
3282+
#define RCC_MCO3_SUPPORT /*!<Support MCO3 */
3283+
#define RCC_MCO3_AF2_SUPPORT /*!<Support MCO3 on Alternate Function AF0 */
32803284

32813285
/******************** Bit definition for RCC_CR register ********************/
32823286
#define RCC_CR_HSION_Pos (0U)
@@ -5030,13 +5034,7 @@ typedef struct
50305034
/*
50315035
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
50325036
*/
5033-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
5034-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
5035-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
5036-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
5037-
#else
50385037
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
5039-
#endif
50405038

50415039
/******************* Bit definition for TIM_CR1 register ********************/
50425040
#define TIM_CR1_CEN_Pos (0U)
@@ -6129,9 +6127,6 @@ typedef struct
61296127
((INSTANCE) == TIM21) || \
61306128
((INSTANCE) == TIM22))
61316129

6132-
/****************** TIM Instances : supporting synchronization ****************/
6133-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
6134-
61356130
/******************* TIM Instances : output(s) OCXEC register *****************/
61366131
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
61376132

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h

+5-10
Original file line numberDiff line numberDiff line change
@@ -3222,8 +3222,12 @@ typedef struct
32223222
/* Reset and Clock Control */
32233223
/* */
32243224
/******************************************************************************/
3225-
3225+
/*
3226+
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
3227+
*/
32263228
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
3229+
#define RCC_MCO3_SUPPORT /*!<Support MCO3 */
3230+
#define RCC_MCO3_AF0_SUPPORT /*!<Support MCO3 on Alternate Function AF2 */
32273231

32283232
/******************** Bit definition for RCC_CR register ********************/
32293233
#define RCC_CR_HSION_Pos (0U)
@@ -5047,13 +5051,7 @@ typedef struct
50475051
/*
50485052
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
50495053
*/
5050-
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
5051-
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
5052-
#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
5053-
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
5054-
#else
50555054
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
5056-
#endif
50575055

50585056
/******************* Bit definition for TIM_CR1 register ********************/
50595057
#define TIM_CR1_CEN_Pos (0U)
@@ -6152,9 +6150,6 @@ typedef struct
61526150
((INSTANCE) == TIM21) || \
61536151
((INSTANCE) == TIM22))
61546152

6155-
/****************** TIM Instances : supporting synchronization ****************/
6156-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
6157-
61586153
/******************* TIM Instances : output(s) OCXEC register *****************/
61596154
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
61606155

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