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When I used CubeMX to verify clock settings of NUCLEO-H563ZI, an error occurred.
I also looked at reference datasheet for H563ZI chip and found some parts that were not optimized.
- ADC/DAC input clock is too high
The maximum clock for ADC/DAC components is 125MHz, but HCLK is 250MHz, so input clock is too high.
As an idea, by setting PLL2 to N = 125
R = 4
it is possible to supply 125MHz from PLL2R to ADC/DAC.
- LPUART clock is low
The LPUART will accept up to 250MHz, but PLL2Q is set to 32MHz, which may result in reduced performance.
I think using a PCLK3 (250MHz) would be fine.
The H563ZI Generic board seems to have same problem.
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