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Merged
merged 2 commits into from
Feb 14, 2022
Merged

Bootloader jump to application #1653

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1559816
system: Restore HSI clock at SystemInit()
ABOSTM Feb 9, 2022
0288818
system: Set VTOR systematically at SystemInit()
ABOSTM Feb 9, 2022
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6 changes: 3 additions & 3 deletions system/STM32F0xx/system_stm32f0xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -184,10 +184,10 @@ void SystemInit(void)
#endif

/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
RCC->CR2 &= (uint32_t)0xFFFFFFFE;

/* Disable all interrupts */
RCC->CIR = 0x00000000U;
/* Disable all interrupts and clear pending bits */
RCC->CIR = (uint32_t)0x00BF0000;

}

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34 changes: 25 additions & 9 deletions system/STM32F1xx/system_stm32f1xx.c
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Expand Up @@ -79,14 +79,33 @@
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */

/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */

/* Note: Following vector table addresses must be defined in line with linker
configuration. */

/*!< Uncomment the following line and change the address
if you need to relocate your vector Table at a custom base address (+ VECT_TAB_OFFSET) */
/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */

/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done by default in Flash. */
/* #define VECT_TAB_SRAM */

#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif

#ifndef VECT_TAB_BASE_ADDRESS
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* VECT_TAB_BASE_ADDRESS */


/**
* @}
Expand Down Expand Up @@ -195,11 +214,8 @@ void SystemInit (void)
#endif /* DATA_IN_ExtSRAM */
#endif

#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
/* Configure the Vector Table location add offset address ------------------*/
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
}

/**
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41 changes: 28 additions & 13 deletions system/STM32F2xx/system_stm32f2xx.c
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Expand Up @@ -66,13 +66,32 @@
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */

/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */

/*!< Uncomment the following line and change the address
if you need to relocate your vector Table at a custom base address (+ VECT_TAB_OFFSET) */
/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */

/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done by default in Flash. */
/* #define VECT_TAB_SRAM */

#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif

#ifndef VECT_TAB_BASE_ADDRESS
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* VECT_TAB_BASE_ADDRESS */

/******************************************************************************/

/**
Expand Down Expand Up @@ -136,30 +155,26 @@ void SystemInit(void)
RCC->CR |= (uint32_t)0x00000001;

/* Reset CFGR register */
RCC->CFGR = 0x00000000;
RCC->CFGR = (uint32_t)0x00000000;

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
RCC->PLLCFGR = (uint32_t)0x24003010;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Disable all interrupts and clear pending bits */
RCC->CIR = (uint32_t)0x00BF0000;

#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */

/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
}

/**
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34 changes: 16 additions & 18 deletions system/STM32F3xx/system_stm32f3xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -84,32 +84,32 @@
/** @addtogroup STM32F3xx_System_Private_Defines
* @{
*/
#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define USER_VECT_TAB_ADDRESS
#endif

/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */

#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line and change the address
if you need to relocate your vector Table at a custom base address (+ VECT_TAB_OFFSET) */
/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */

/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
in Sram else user remap will be done by default in Flash. */
/* #define VECT_TAB_SRAM */

#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif

#ifndef VECT_TAB_BASE_ADDRESS
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /* VECT_TAB_BASE_ADDRESS */

/******************************************************************************/
/**
Expand Down Expand Up @@ -190,13 +190,11 @@ void SystemInit(void)
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
RCC->CFGR3 &= 0xFF00FCCCU;

/* Disable all interrupts */
RCC->CIR = 0x00000000U;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U;

/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
}

/**
Expand Down
44 changes: 23 additions & 21 deletions system/STM32F4xx/system_stm32f4xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -79,32 +79,33 @@
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */

#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define USER_VECT_TAB_ADDRESS
#endif

/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */

#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line and change the address
if you need to relocate your vector Table at a custom base address (+ VECT_TAB_OFFSET) */
/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */

/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
in Sram else user remap will be done by default in Flash. */
/* #define VECT_TAB_SRAM */

#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif

#ifndef VECT_TAB_BASE_ADDRESS
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /* VECT_TAB_BASE_ADDRESS */


/******************************************************************************/

/**
Expand Down Expand Up @@ -171,28 +172,29 @@ void SystemInit(void)
RCC->CR |= (uint32_t)0x00000001;

/* Reset CFGR register */
RCC->CFGR = 0x00000000;
RCC->CFGR = (uint32_t)0x00000000;

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
RCC->PLLCFGR = (uint32_t)0x24003010;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined(RCC_CIR_PLLSAIRDYC)
RCC->CIR = (uint32_t)0x00FF0000;
#else
RCC->CIR = (uint32_t)0x00BF0000;
#endif

#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */

/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
}

/**
Expand Down
35 changes: 17 additions & 18 deletions system/STM32F7xx/system_stm32f7xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -63,31 +63,32 @@
*/

/************************* Miscellaneous Configuration ************************/
/* Note: Following vector table addresses must be defined in line with linker
configuration. */

/*!< Uncomment the following line and change the address
if you need to relocate your vector Table at a custom base address (+ VECT_TAB_OFFSET) */
/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */

/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done by default in Flash. */
/* #define VECT_TAB_SRAM */

#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define USER_VECT_TAB_ADDRESS
#endif

/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Define USER_VECT_TAB_ADDRESS line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Define VECT_TAB_SRAM if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
#ifndef VECT_TAB_BASE_ADDRESS
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /* VECT_TAB_BASE_ADDRESS */

/******************************************************************************/

/**
Expand Down Expand Up @@ -152,25 +153,23 @@ void SystemInit(void)
RCC->CR |= (uint32_t)0x00000001;

/* Reset CFGR register */
RCC->CFGR = 0x00000000;
RCC->CFGR = (uint32_t)0x00000000;

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
RCC->PLLCFGR = (uint32_t)0x24003010;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Disable all interrupts and clear pending bits */
RCC->CIR = (uint32_t)0x00FF0000;


/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
}

/**
Expand Down
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