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Jessica Paquette
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[AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg
When you encounter a G_TRUNC, you are moving from a larger type to a smaller type. Asking for the i-th bit on a larger value is the same as asking for the i-th bit on a smaller value. So, we should always be able to walk through G_TRUNC when computing the bit for a TB(N)Z. Differential Revision: https://reviews.llvm.org/D73748
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llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

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@@ -998,7 +998,11 @@ static Register getTestBitReg(Register Reg, MachineRegisterInfo &MRI) {
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Register NextReg;
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// (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
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if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT)
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//
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// (tbz (trunc x), b) -> (tbz x, b) is always safe, because the bit number
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// on the truncated x is the same as the bit number on x.
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if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT ||
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Opc == TargetOpcode::G_TRUNC)
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NextReg = MI->getOperand(1).getReg();
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// Did we find something worth folding?
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@@ -0,0 +1,35 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: fold_trunc
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fold_trunc
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64all = COPY $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: TBNZW [[COPY1]], 3, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%bit:gpr(s32) = G_CONSTANT i32 8
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%zero:gpr(s32) = G_CONSTANT i32 0
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%fold_me:gpr(s32) = G_TRUNC %copy(s64)
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%and:gpr(s32) = G_AND %fold_me, %bit
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%cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR

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