ESESC: A Fast Multicore Simulator

A Fast DNN Accelerator Design Space Exploration Framework.

My solutions of Computer Systems: A Programmer’s Perspective, Third Edition (CS:APP3e) book, the text book for the course, CMU15-213: Introduction to Computer Systems.

HHRT: Hybrid Hierarchical Runtime library

Hardware compression for memory

Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies

A high-performance cache and memory hierarchy simulator built with modern C++17. Features configurable cache levels, advanced prefetching, MESI protocol, and detailed statistics. Ideal for computer architecture education, research, and performance analysis.

A superscalar out-of‐order architectural simulator (With Memory Hierarchy).

Implementation of Hierarchy Oblivious Algorithms

(ECE) A collection of helper scripts for the assignments for the course "Advanced Computer Architecture" [3.4.37.8]

A loop test performance simulator for cache memories

The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.

Papyrus: Parallel Aggregate Persistent Storage

A simulator of cache system behavior.

Memory Hierarchy - Branch Prediction and Predictors - Cache Coherence Protocols | Advanced Topics in Computer Architecture at ECE NTUA

A bash shell script to show information about memory hierarchy. PT-br: Um script shell para mostrar informações sobre a hierarquia de memória.

Assembly MIPS - Pipelined Datapath - Memory Hierarchy - Virtual Memory | Computer Architecture at ECE NTUA

CSE 614 Term Project