[DAG] Match fixed width ISD::AVGFLOORS + ISD::AVGCEILS patterns

[RKSimon]

Followup to #84749 and #84753

We can match the signed AVG variants in a similar way:

define i4 @src_avgfloors(i4 %a0, i4 %a1)  {
  %and = and i4 %a0, %a1
  %xor = xor i4 %a0, %a1
  %srl = ashr i4 %xor, 1
  %res = add i4 %and, %srl
  ret i4 %res
}
define i4 @src_avgceils(i4 %a0, i4 %a1)  {
  %or = or i4 %a0, %a1
  %xor = xor i4 %a0, %a1
  %srl = ashr i4 %xor, 1
  %res = sub i4 %or, %srl
  ret i4 %res
}

Alive2: https://alive2.llvm.org/ce/z/L4yGAx

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

1. In the comments of the issue, request for it to be assigned to you.
2. Fix the issue locally.
3. Run the test suite locally. Remember that the subdirectories under test/ create fine-grained testing targets, so you can e.g. use make check-clang-ast to only run Clang's AST tests.
4. Create a Git commit.
5. Run git clang-format HEAD~1 to format your changes.
6. Open a pull request to the upstream repository on GitHub. Detailed instructions can be found in GitHub's documentation.

If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

Followup to #84749 and #84753

We can match the signed AVG variants in a similar way:

define i4 @<!-- -->src_avgfloors(i4 %a0, i4 %a1)  {
  %and = and i4 %a0, %a1
  %xor = xor i4 %a0, %a1
  %srl = ashr i4 %xor, 1
  %res = add i4 %and, %srl
  ret i4 %res
}
define i4 @<!-- -->src_avgceils(i4 %a0, i4 %a1)  {
  %or = or i4 %a0, %a1
  %xor = xor i4 %a0, %a1
  %srl = ashr i4 %xor, 1
  %res = sub i4 %or, %srl
  ret i4 %res
}

Alive2: https://alive2.llvm.org/ce/z/L4yGAx

[houndlord]

I would like to work on this