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[RISCV] Fix InsnCI register type #100113

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Merged
merged 1 commit into from
Jul 23, 2024
Merged

[RISCV] Fix InsnCI register type #100113

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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoC.td
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Original file line number Diff line number Diff line change
Expand Up @@ -764,9 +764,9 @@ def InsnCR : DirectiveInsnCR<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode,
uimm4:$funct4,
AnyReg:$rs2),
"$opcode, $funct4, $rd, $rs2">;
def InsnCI : DirectiveInsnCI<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
simm6:$imm6),
def InsnCI : DirectiveInsnCI<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
simm6:$imm6),
"$opcode, $funct3, $rd, $imm6">;
def InsnCIW : DirectiveInsnCIW<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
Expand Down Expand Up @@ -818,7 +818,7 @@ def : InstAlias<".insn_cr $opcode, $funct4, $rd, $rs2",
(InsnCR AnyReg:$rd, uimm2_opcode:$opcode, uimm4:$funct4,
AnyReg:$rs2)>;
def : InstAlias<".insn_ci $opcode, $funct3, $rd, $imm6",
(InsnCI AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
(InsnCI AnyReg:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
simm6:$imm6)>;
def : InstAlias<".insn_ciw $opcode, $funct3, $rd, $imm8",
(InsnCIW AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
Expand Down
10 changes: 10 additions & 0 deletions llvm/test/MC/RISCV/insn_c.s
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,16 @@ target:
# CHECK-OBJ: c.addi a0, 0xd
.insn ci C1, 0, a0, 13

# CHECK-ASM: .insn ci 1, 0, a6, 13
# CHECK-ASM: encoding: [0x35,0x08]
# CHECK-OBJ: c.addi a6, 0xd
.insn ci 1, 0, a6, 13

# CHECK-ASM: .insn ci 1, 0, a6, 13
# CHECK-ASM: encoding: [0x35,0x08]
# CHECK-OBJ: c.addi a6, 0xd
.insn ci C1, 0, a6, 13

# CHECK-ASM: .insn ciw 0, 0, a0, 13
# CHECK-ASM: encoding: [0xa8,0x01]
# CHECK-OBJ: c.addi4spn a0, sp, 0xc8
Expand Down
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