[Xtensa] Implement branch analysis. #110959
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| case Xtensa::BGEI: | ||
| case Xtensa::BGEUI: | ||
| return MI.getOperand(2).getMBB(); | ||
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Currently this code is removed as redundant.
| bool XtensaInstrInfo::analyzeBranch(MachineBasicBlock &MBB, | ||
| MachineBasicBlock *&TBB, | ||
| MachineBasicBlock *&FBB, | ||
| SmallVectorImpl<MachineOperand> &Cond, | ||
| bool AllowModify = false) const { |
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This family of functions should be implemented independently of branch relaxation. They're more used for branch folding
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Thank you for comment. Is it ok if I will correct this PR and remove branch relaxation functionality? The PR then will contain only branch analysis implementation.
| // FIXME: A virtual register must be used initially, as the register | ||
| // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch | ||
| // uses the same workaround). | ||
| Register ScratchReg = MRI.createVirtualRegister(&Xtensa::ARRegClass); |
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I think this got fixed actually. The workaround might still be there though
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Currently this code is removed as redundant.
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| const DebugLoc &DL, | ||
| int *BytesAdded = nullptr) const override; | ||
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| unsigned InsertBranchAtInst(MachineBasicBlock &MBB, |
| if (I->isDebugValue()) | ||
| continue; |
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I prepared new test which checks analyzeBranch and reverseBranchCondition functionality. I hope I understand your comment correctly.
| case Xtensa::BLTUI: | ||
| Cond[0].setImm(Xtensa::BGEUI); | ||
| return false; | ||
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Inconsistent blank lines here and a few other places
| SmallVectorImpl<MachineOperand> &Cond) const { | ||
| assert(Cond.size() <= 4 && "Invalid branch condition!"); | ||
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| switch (Cond[0].getImm()) { |
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Not sure all of these are tested?
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I tested most of cases for reverseBranchCondition and it seems it works correctly.
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