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[RISCV] Sink ordered reduction check into FAdd. NFC #114180

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Merged
merged 2 commits into from
Oct 31, 2024

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ElvisWang123
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llvmbot commented Oct 30, 2024

@llvm/pr-subscribers-backend-risc-v

Author: Elvis Wang (ElvisWang123)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/114180.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+1-1)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 395baa5f1aab99..bfc3f5b29a2aaa 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1552,7 +1552,7 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
   }
 
   // IR Reduction is composed by two vmv and one rvv reduction instruction.
-  if (TTI::requiresOrderedReduction(FMF)) {
+  if (TTI::requiresOrderedReduction(FMF) && ElementTy->isFloatingPointTy()) {
     Opcodes.push_back(RISCV::VFMV_S_F);
     for (unsigned i = 0; i < LT.first.getValue(); i++)
       Opcodes.push_back(RISCV::VFREDOSUM_VS);

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preames commented Oct 30, 2024

What is the point of this change? Only floating point reductions should return true for requiresOrderedReduction?

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What is the point of this change? Only floating point reductions should return true for requiresOrderedReduction?

Without the check querying the getArithmeticReductionCost() by reduce.add reduce.and ... integer reductions without reassoc flag will fall into it. And it will return the cost of the floating point ordered reduction.

I found this issue in the #114184. When we query the cost model and always pass the FMF flags from the IntrinsicCostAttributes, it always return the cost of FP ordered reduction.

I thought it is more user friendly to check if it is floating point type and user can call getArithmeticReductionCost() without dropping FMF flags when it is integer type.

@preames preames closed this Oct 30, 2024
@preames preames reopened this Oct 30, 2024
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preames commented Oct 30, 2024

Mostly summarizing my investigation for future reference.

The way this works for the current reduce.* intrinsics is that BasicTTI dispatches these to getArithmeticReductionCost and getMinMaxReductionCost respective. BasicTTI distinguishes fadd/fmul from the other arithmetic, and specifically passes None for the FMF on non-FP arithmetics. It does pass the FMF to the MinMax variant, but since there are no ordered min/max variants, that doesn't apply.

@@ -1552,7 +1552,7 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
}

// IR Reduction is composed by two vmv and one rvv reduction instruction.
if (TTI::requiresOrderedReduction(FMF)) {
if (TTI::requiresOrderedReduction(FMF) && ElementTy->isFloatingPointTy()) {
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I think a cleaner way to express this change is to simply sink the check for requiresOrderedReduction under the FADD case in the switch below. That's the only supported reduction kind with an ordered variant.

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I am worried about transformations using getArithmeticReductionCost() directly to query the instruction cost and not dropping the FMF flags with integer type.
After investigation, all query will not return wrong instruction cost currently.

I am fine to close this PR.

@ElvisWang123 ElvisWang123 force-pushed the fix-reduction-cost-fmf branch from d6b3e45 to 24ecef8 Compare October 30, 2024 16:55
@ElvisWang123 ElvisWang123 changed the title [RISCV] Only calculate ordered reduction with FloatingPoint type. NFC [RISCV] Sink ordered reduction check into FAdd. NFC Oct 30, 2024
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LGTM

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LGTM, I'll rework #114250 after this lands

@ElvisWang123 ElvisWang123 force-pushed the fix-reduction-cost-fmf branch from 24ecef8 to 5af5e32 Compare October 31, 2024 01:41
@ElvisWang123 ElvisWang123 merged commit a8575c1 into llvm:main Oct 31, 2024
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@ElvisWang123 ElvisWang123 deleted the fix-reduction-cost-fmf branch October 31, 2024 05:35
smallp-o-p pushed a commit to smallp-o-p/llvm-project that referenced this pull request Nov 3, 2024
NoumanAmir657 pushed a commit to NoumanAmir657/llvm-project that referenced this pull request Nov 4, 2024
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4 participants